<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>i3c: Overview</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">i3c
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
      <li><a href="pages.html"><span>Examples</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('group___overview.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#nested-classes">Data Structures</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#typedef-members">Typedefs</a> &#124;
<a href="#func-members">Functions</a> &#124;
<a href="#var-members">Variables</a>  </div>
  <div class="headertitle">
<div class="title">Overview</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the device.  <a href="struct_x_i3c___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i3c___slave_info.html">XI3c_SlaveInfo</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> slave data.  <a href="struct_x_i3c___slave_info.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_i3c.html">XI3c</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> driver instance data.  <a href="struct_x_i3c.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga274b0856bce55f704b8ad00e939d8898"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga274b0856bce55f704b8ad00e939d8898">XI3C_H</a></td></tr>
<tr class="memdesc:ga274b0856bce55f704b8ad00e939d8898"><td class="mdescLeft">&#160;</td><td class="mdescRight">by using protection macros  <a href="#ga274b0856bce55f704b8ad00e939d8898">More...</a><br/></td></tr>
<tr class="separator:ga274b0856bce55f704b8ad00e939d8898"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga199da98d8ddcd495482b436d294ec75d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga199da98d8ddcd495482b436d294ec75d">TIMEOUT_COUNTER</a>&#160;&#160;&#160;2000000U</td></tr>
<tr class="memdesc:ga199da98d8ddcd495482b436d294ec75d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait for 2 sec in worst case.  <a href="#ga199da98d8ddcd495482b436d294ec75d">More...</a><br/></td></tr>
<tr class="separator:ga199da98d8ddcd495482b436d294ec75d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab00798fa6acd361fcd8c15ef50065bde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab00798fa6acd361fcd8c15ef50065bde">XI3c_BusIsBusy</a>(BaseAddress)&#160;&#160;&#160;(<a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>) &amp; <a class="el" href="group___overview.html#ga07f073cf0ff84797b4d805541b4fbec7">XI3C_SR_BUS_BUSY_MASK</a>)</td></tr>
<tr class="memdesc:gab00798fa6acd361fcd8c15ef50065bde"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks whether the I3C bus is busy.  <a href="#gab00798fa6acd361fcd8c15ef50065bde">More...</a><br/></td></tr>
<tr class="separator:gab00798fa6acd361fcd8c15ef50065bde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga081b8df5809a3e6efc26ac7fe120c90b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga081b8df5809a3e6efc26ac7fe120c90b">XI3c_GetDynaAddr</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga081b8df5809a3e6efc26ac7fe120c90b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the dynamic address of the I3C.  <a href="#ga081b8df5809a3e6efc26ac7fe120c90b">More...</a><br/></td></tr>
<tr class="separator:ga081b8df5809a3e6efc26ac7fe120c90b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7efd0f29eba1bd3d20f9ecdf62f14c0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7efd0f29eba1bd3d20f9ecdf62f14c0b">XI3c_SetSclHighTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga7efd0f29eba1bd3d20f9ecdf62f14c0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets scl high time of I3C.  <a href="#ga7efd0f29eba1bd3d20f9ecdf62f14c0b">More...</a><br/></td></tr>
<tr class="separator:ga7efd0f29eba1bd3d20f9ecdf62f14c0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4c3c52633de88fa131ad59aef0870a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf4c3c52633de88fa131ad59aef0870a9">XI3c_GetSclHighTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf4c3c52633de88fa131ad59aef0870a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets scl high time of I3C.  <a href="#gaf4c3c52633de88fa131ad59aef0870a9">More...</a><br/></td></tr>
<tr class="separator:gaf4c3c52633de88fa131ad59aef0870a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96598e0e4ac5fc98159cbbe34f266976"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga96598e0e4ac5fc98159cbbe34f266976">XI3c_SetSclLowTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga96598e0e4ac5fc98159cbbe34f266976"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets scl low time of I3C.  <a href="#ga96598e0e4ac5fc98159cbbe34f266976">More...</a><br/></td></tr>
<tr class="separator:ga96598e0e4ac5fc98159cbbe34f266976"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga761aaa270ed25b3c92f7f9212ba947ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga761aaa270ed25b3c92f7f9212ba947ea">XI3c_GetSclLowTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga761aaa270ed25b3c92f7f9212ba947ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets scl low time of I3C.  <a href="#ga761aaa270ed25b3c92f7f9212ba947ea">More...</a><br/></td></tr>
<tr class="separator:ga761aaa270ed25b3c92f7f9212ba947ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ca247fdf2e014bc7974c8789f5cb1fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3ca247fdf2e014bc7974c8789f5cb1fa">XI3c_SetSdaHoldTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga3ca247fdf2e014bc7974c8789f5cb1fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets sda hold time of I3C.  <a href="#ga3ca247fdf2e014bc7974c8789f5cb1fa">More...</a><br/></td></tr>
<tr class="separator:ga3ca247fdf2e014bc7974c8789f5cb1fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00bd308ab29e0112b613fa5001366a2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga00bd308ab29e0112b613fa5001366a2c">XI3c_GetSdaHoldTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga00bd308ab29e0112b613fa5001366a2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets sda hold time of I3C.  <a href="#ga00bd308ab29e0112b613fa5001366a2c">More...</a><br/></td></tr>
<tr class="separator:ga00bd308ab29e0112b613fa5001366a2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8879a5913307a7fef1085a98a985306b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8879a5913307a7fef1085a98a985306b">XI3c_SetBusIdleTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga8879a5913307a7fef1085a98a985306b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets bus idle time of I3C.  <a href="#ga8879a5913307a7fef1085a98a985306b">More...</a><br/></td></tr>
<tr class="separator:ga8879a5913307a7fef1085a98a985306b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf139462f725a3c0b3a8a3cedfa204898"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf139462f725a3c0b3a8a3cedfa204898">XI3c_GetBusIdleTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf139462f725a3c0b3a8a3cedfa204898"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets bus idle time of I3C.  <a href="#gaf139462f725a3c0b3a8a3cedfa204898">More...</a><br/></td></tr>
<tr class="separator:gaf139462f725a3c0b3a8a3cedfa204898"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f4c510d9d1c0d109cff9051c15423fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4f4c510d9d1c0d109cff9051c15423fc">XI3c_SetTsuStartTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga4f4c510d9d1c0d109cff9051c15423fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets Tsu Start time of I3C.  <a href="#ga4f4c510d9d1c0d109cff9051c15423fc">More...</a><br/></td></tr>
<tr class="separator:ga4f4c510d9d1c0d109cff9051c15423fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbf0a51b190414a36c9d1407cdbfb53e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacbf0a51b190414a36c9d1407cdbfb53e">XI3c_GetTsuStartTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:gacbf0a51b190414a36c9d1407cdbfb53e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Tsu Start time of I3C.  <a href="#gacbf0a51b190414a36c9d1407cdbfb53e">More...</a><br/></td></tr>
<tr class="separator:gacbf0a51b190414a36c9d1407cdbfb53e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad40e322019eadf7b34ba6ff527097295"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad40e322019eadf7b34ba6ff527097295">XI3c_SetThdStartTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:gad40e322019eadf7b34ba6ff527097295"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets Thd Start time of I3C.  <a href="#gad40e322019eadf7b34ba6ff527097295">More...</a><br/></td></tr>
<tr class="separator:gad40e322019eadf7b34ba6ff527097295"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e759c8db730bde42150bee0ad9f423a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3e759c8db730bde42150bee0ad9f423a">XI3c_GetThdStartTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga3e759c8db730bde42150bee0ad9f423a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets Thd Start time.  <a href="#ga3e759c8db730bde42150bee0ad9f423a">More...</a><br/></td></tr>
<tr class="separator:ga3e759c8db730bde42150bee0ad9f423a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd55de5f0c3287b23bdc9ee3b1981fd4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafd55de5f0c3287b23bdc9ee3b1981fd4">XI3c_SetTsuStopTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:gafd55de5f0c3287b23bdc9ee3b1981fd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets Tsu Stop time of I3C.  <a href="#gafd55de5f0c3287b23bdc9ee3b1981fd4">More...</a><br/></td></tr>
<tr class="separator:gafd55de5f0c3287b23bdc9ee3b1981fd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf75ae078e7f9fc0d9ba22c01a5636b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacf75ae078e7f9fc0d9ba22c01a5636b2">XI3c_GetTsuStopTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:gacf75ae078e7f9fc0d9ba22c01a5636b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Tsu Stop time of I3C.  <a href="#gacf75ae078e7f9fc0d9ba22c01a5636b2">More...</a><br/></td></tr>
<tr class="separator:gacf75ae078e7f9fc0d9ba22c01a5636b2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d1aac5f2db8f3623f1897f92ad8425c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1d1aac5f2db8f3623f1897f92ad8425c">XI3c_SetSclOdHighTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:ga1d1aac5f2db8f3623f1897f92ad8425c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets Scl open drain high time of I3C.  <a href="#ga1d1aac5f2db8f3623f1897f92ad8425c">More...</a><br/></td></tr>
<tr class="separator:ga1d1aac5f2db8f3623f1897f92ad8425c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09c6e2c3a3d2a2af74cbe60aae6d8e0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga09c6e2c3a3d2a2af74cbe60aae6d8e0a">XI3c_GetSclOdHighTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga09c6e2c3a3d2a2af74cbe60aae6d8e0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Scl open drain high time of I3C.  <a href="#ga09c6e2c3a3d2a2af74cbe60aae6d8e0a">More...</a><br/></td></tr>
<tr class="separator:ga09c6e2c3a3d2a2af74cbe60aae6d8e0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6571c88c0dfe0e735a30264e041c809"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad6571c88c0dfe0e735a30264e041c809">XI3c_SetSclOdLowTime</a>(InstancePtr, Val)</td></tr>
<tr class="memdesc:gad6571c88c0dfe0e735a30264e041c809"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets Scl open drain low time of I3C.  <a href="#gad6571c88c0dfe0e735a30264e041c809">More...</a><br/></td></tr>
<tr class="separator:gad6571c88c0dfe0e735a30264e041c809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1e4d1386198f402fa21ad9c36ea60f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac1e4d1386198f402fa21ad9c36ea60f2">XI3c_GetSclOdLowTime</a>(InstancePtr)</td></tr>
<tr class="memdesc:gac1e4d1386198f402fa21ad9c36ea60f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Scl open drain low time of I3C.  <a href="#gac1e4d1386198f402fa21ad9c36ea60f2">More...</a><br/></td></tr>
<tr class="separator:gac1e4d1386198f402fa21ad9c36ea60f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34208c49e1fb181e5d75006a27cee535"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga34208c49e1fb181e5d75006a27cee535">XI3c_GetRevisionNumber</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga34208c49e1fb181e5d75006a27cee535"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Core Revision number of I3C.  <a href="#ga34208c49e1fb181e5d75006a27cee535">More...</a><br/></td></tr>
<tr class="separator:ga34208c49e1fb181e5d75006a27cee535"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2a15d20998f93c82b2ea5803a407d8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf2a15d20998f93c82b2ea5803a407d8c">XI3c_GetResponseData</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf2a15d20998f93c82b2ea5803a407d8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets Response data of I3C.  <a href="#gaf2a15d20998f93c82b2ea5803a407d8c">More...</a><br/></td></tr>
<tr class="separator:gaf2a15d20998f93c82b2ea5803a407d8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7029965ea1ab665e22bd199cefd9e2a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7029965ea1ab665e22bd199cefd9e2a4">XI3c_GetErrorStatus</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7029965ea1ab665e22bd199cefd9e2a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets error status from response of I3C.  <a href="#ga7029965ea1ab665e22bd199cefd9e2a4">More...</a><br/></td></tr>
<tr class="separator:ga7029965ea1ab665e22bd199cefd9e2a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6707c3c86ecbb35f037252f3db9b57aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6707c3c86ecbb35f037252f3db9b57aa">XI3c_IsDyncAddrAssigned</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga6707c3c86ecbb35f037252f3db9b57aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the dynamic address assignment status of I3C in slave mode.  <a href="#ga6707c3c86ecbb35f037252f3db9b57aa">More...</a><br/></td></tr>
<tr class="separator:ga6707c3c86ecbb35f037252f3db9b57aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5e1fadfb7307f4993cc96f32efe43e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad5e1fadfb7307f4993cc96f32efe43e4">XI3c_IsRespAvailable</a>(InstancePtr)</td></tr>
<tr class="memdesc:gad5e1fadfb7307f4993cc96f32efe43e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the response status of I3C.  <a href="#gad5e1fadfb7307f4993cc96f32efe43e4">More...</a><br/></td></tr>
<tr class="separator:gad5e1fadfb7307f4993cc96f32efe43e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad62fd667f9befb43452d4d8627501520"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad62fd667f9befb43452d4d8627501520">XI3c_SetDeviceStatus</a>(InstancePtr, Format1, Format2)</td></tr>
<tr class="memdesc:gad62fd667f9befb43452d4d8627501520"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets device status of I3C.  <a href="#gad62fd667f9befb43452d4d8627501520">More...</a><br/></td></tr>
<tr class="separator:gad62fd667f9befb43452d4d8627501520"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ea989327a7525174a52188888e4434f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6ea989327a7525174a52188888e4434f">XI3c_SetMaxDataSpeed</a>(InstancePtr, Format1, Format3)</td></tr>
<tr class="memdesc:ga6ea989327a7525174a52188888e4434f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets device Max data speed.  <a href="#ga6ea989327a7525174a52188888e4434f">More...</a><br/></td></tr>
<tr class="separator:ga6ea989327a7525174a52188888e4434f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71646fcfb10ac4f32b64f559fc5bc355"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga71646fcfb10ac4f32b64f559fc5bc355">XI3c_SetCapsFormat1</a>(InstancePtr, Cap1, Cap2, Cap3, Cap4)</td></tr>
<tr class="memdesc:ga71646fcfb10ac4f32b64f559fc5bc355"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets device capabilities format1.  <a href="#ga71646fcfb10ac4f32b64f559fc5bc355">More...</a><br/></td></tr>
<tr class="separator:ga71646fcfb10ac4f32b64f559fc5bc355"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dbc4d41771a2b6ca9da3c230b172562"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0dbc4d41771a2b6ca9da3c230b172562">XI3c_SetCapsFormat2</a>(InstancePtr, Cap1, Cap2)</td></tr>
<tr class="memdesc:ga0dbc4d41771a2b6ca9da3c230b172562"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets device capabilities format2.  <a href="#ga0dbc4d41771a2b6ca9da3c230b172562">More...</a><br/></td></tr>
<tr class="separator:ga0dbc4d41771a2b6ca9da3c230b172562"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3f42f6b73f1536013fce8bef9a8b089c">XI3C_HW_H_</a></td></tr>
<tr class="memdesc:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="#ga3f42f6b73f1536013fce8bef9a8b089c">More...</a><br/></td></tr>
<tr class="separator:ga3f42f6b73f1536013fce8bef9a8b089c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1cd52261485c5865d5b0ff1fc16e9fa9">XI3C_BASEADDR</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000.  <a href="#ga1cd52261485c5865d5b0ff1fc16e9fa9">More...</a><br/></td></tr>
<tr class="separator:ga1cd52261485c5865d5b0ff1fc16e9fa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:ga7a0b155b789c03dd574c94bbf0d195db"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7a0b155b789c03dd574c94bbf0d195db">XI3c_IntrHandler</a> )(u32 StatusEvent)</td></tr>
<tr class="memdesc:ga7a0b155b789c03dd574c94bbf0d195db"><td class="mdescLeft">&#160;</td><td class="mdescRight">The handler data type allows the user to define a callback function to respond to interrupt events in the system.  <a href="#ga7a0b155b789c03dd574c94bbf0d195db">More...</a><br/></td></tr>
<tr class="separator:ga7a0b155b789c03dd574c94bbf0d195db"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga52d0b05e4f81129c7a75cefdf0ef5621"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga52d0b05e4f81129c7a75cefdf0ef5621">XI3c_ConfigIbi</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 DevCount)</td></tr>
<tr class="memdesc:ga52d0b05e4f81129c7a75cefdf0ef5621"><td class="mdescLeft">&#160;</td><td class="mdescRight">This configure target address and BCR register values of available devices to the controller RAM.  <a href="#ga52d0b05e4f81129c7a75cefdf0ef5621">More...</a><br/></td></tr>
<tr class="separator:ga52d0b05e4f81129c7a75cefdf0ef5621"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa01a28908016aac835dd4493a0c6413e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa01a28908016aac835dd4493a0c6413e">XI3C_BusInit</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa01a28908016aac835dd4493a0c6413e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> slaves devices by disable/enable events and reset dynamic addresses.  <a href="#gaa01a28908016aac835dd4493a0c6413e">More...</a><br/></td></tr>
<tr class="separator:gaa01a28908016aac835dd4493a0c6413e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a6f3237b5eecb5d9144c3254dbab088"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, <a class="el" href="struct_x_i3c___config.html">XI3c_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
<tr class="memdesc:ga3a6f3237b5eecb5d9144c3254dbab088"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance such that the driver is ready to use.  <a href="#ga3a6f3237b5eecb5d9144c3254dbab088">More...</a><br/></td></tr>
<tr class="separator:ga3a6f3237b5eecb5d9144c3254dbab088"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb601913b993b4c23cb89306aa630be5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd)</td></tr>
<tr class="memdesc:gafb601913b993b4c23cb89306aa630be5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fill I3C Command fifo.  <a href="#gafb601913b993b4c23cb89306aa630be5">More...</a><br/></td></tr>
<tr class="separator:gafb601913b993b4c23cb89306aa630be5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58e612565bbd976e98eac6753ad1ed9f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga58e612565bbd976e98eac6753ad1ed9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fill I3C Write Tx FIFO.  <a href="#ga58e612565bbd976e98eac6753ad1ed9f">More...</a><br/></td></tr>
<tr class="separator:ga58e612565bbd976e98eac6753ad1ed9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2aab26f4e34599f22921e263af12e0d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad2aab26f4e34599f22921e263af12e0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read RX I3C FIFO.  <a href="#gad2aab26f4e34599f22921e263af12e0d">More...</a><br/></td></tr>
<tr class="separator:gad2aab26f4e34599f22921e263af12e0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87d285dd413cf579d43a6eda306619ce"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 DynaAddr[], u8 DevCount)</td></tr>
<tr class="memdesc:ga87d285dd413cf579d43a6eda306619ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends dynamic Address Assignment for available devices.  <a href="#ga87d285dd413cf579d43a6eda306619ce">More...</a><br/></td></tr>
<tr class="separator:ga87d285dd413cf579d43a6eda306619ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8212bca3426c2ca6a284e5de2a5a9180"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8212bca3426c2ca6a284e5de2a5a9180">XI3c_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:ga8212bca3426c2ca6a284e5de2a5a9180"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the unique device ID.  <a href="#ga8212bca3426c2ca6a284e5de2a5a9180">More...</a><br/></td></tr>
<tr class="separator:ga8212bca3426c2ca6a284e5de2a5a9180"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga822775f0526bd47739bdf842954d874f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga822775f0526bd47739bdf842954d874f">XI3c_SendTransferCmd</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd, u8 Data)</td></tr>
<tr class="memdesc:ga822775f0526bd47739bdf842954d874f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends the command.  <a href="#ga822775f0526bd47739bdf842954d874f">More...</a><br/></td></tr>
<tr class="separator:ga822775f0526bd47739bdf842954d874f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bdcc22a96e0b2be5e806b29761cc83a"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u32 SclkHz, u8 Mode)</td></tr>
<tr class="memdesc:ga8bdcc22a96e0b2be5e806b29761cc83a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets I3C Scl clock frequency.  <a href="#ga8bdcc22a96e0b2be5e806b29761cc83a">More...</a><br/></td></tr>
<tr class="separator:ga8bdcc22a96e0b2be5e806b29761cc83a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa8b632c4926c7125ffe178ec72a167db"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa8b632c4926c7125ffe178ec72a167db">XI3c_SetStatusHandler</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, <a class="el" href="group___overview.html#ga7a0b155b789c03dd574c94bbf0d195db">XI3c_IntrHandler</a> FunctionPtr)</td></tr>
<tr class="memdesc:gaa8b632c4926c7125ffe178ec72a167db"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software.  <a href="#gaa8b632c4926c7125ffe178ec72a167db">More...</a><br/></td></tr>
<tr class="separator:gaa8b632c4926c7125ffe178ec72a167db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0d816198d0abc6dabb332390fbe5c79"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:gab0d816198d0abc6dabb332390fbe5c79"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a interrupt mode send in master mode.  <a href="#gab0d816198d0abc6dabb332390fbe5c79">More...</a><br/></td></tr>
<tr class="separator:gab0d816198d0abc6dabb332390fbe5c79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65bbec96638b9e2f5627452ac9a9ae48"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga65bbec96638b9e2f5627452ac9a9ae48">XI3c_MasterRecv</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:ga65bbec96638b9e2f5627452ac9a9ae48"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a interrupt mode receive in master mode.  <a href="#ga65bbec96638b9e2f5627452ac9a9ae48">More...</a><br/></td></tr>
<tr class="separator:ga65bbec96638b9e2f5627452ac9a9ae48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga268011500642adc668ce75abbe555a6a"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga268011500642adc668ce75abbe555a6a">XI3c_MasterSendPolled</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:ga268011500642adc668ce75abbe555a6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a polled mode send in master mode.  <a href="#ga268011500642adc668ce75abbe555a6a">More...</a><br/></td></tr>
<tr class="separator:ga268011500642adc668ce75abbe555a6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga838caa68513d3391c4f3e85705671f46"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga838caa68513d3391c4f3e85705671f46">XI3c_MasterRecvPolled</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, XI3c_Cmd *Cmd, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:ga838caa68513d3391c4f3e85705671f46"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a polled mode receive in master mode.  <a href="#ga838caa68513d3391c4f3e85705671f46">More...</a><br/></td></tr>
<tr class="separator:ga838caa68513d3391c4f3e85705671f46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c4e3e321553508d75097bebe04d0cf5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga8c4e3e321553508d75097bebe04d0cf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">The interrupt handler for the master mode.  <a href="#ga8c4e3e321553508d75097bebe04d0cf5">More...</a><br/></td></tr>
<tr class="separator:ga8c4e3e321553508d75097bebe04d0cf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0d7f9bd9e10d5de348154d823d7bea0"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae0d7f9bd9e10d5de348154d823d7bea0">XI3c_IbiRecv</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr)</td></tr>
<tr class="memdesc:gae0d7f9bd9e10d5de348154d823d7bea0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function setup for receive during IBI in interrupt mode.  <a href="#gae0d7f9bd9e10d5de348154d823d7bea0">More...</a><br/></td></tr>
<tr class="separator:gae0d7f9bd9e10d5de348154d823d7bea0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09a7b530e37d1df22d1373966e826cf2"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr)</td></tr>
<tr class="memdesc:ga09a7b530e37d1df22d1373966e826cf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives data during IBI in polled mode.  <a href="#ga09a7b530e37d1df22d1373966e826cf2">More...</a><br/></td></tr>
<tr class="separator:ga09a7b530e37d1df22d1373966e826cf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28021172cfe5d1d3dfb20e8f3f58c94f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga28021172cfe5d1d3dfb20e8f3f58c94f">XI3c_SlaveSend</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:ga28021172cfe5d1d3dfb20e8f3f58c94f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a interrupt mode send in slave mode.  <a href="#ga28021172cfe5d1d3dfb20e8f3f58c94f">More...</a><br/></td></tr>
<tr class="separator:ga28021172cfe5d1d3dfb20e8f3f58c94f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9808772192d0f16adaf33e61b784e3a3"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9808772192d0f16adaf33e61b784e3a3">XI3c_SlaveRecv</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr)</td></tr>
<tr class="memdesc:ga9808772192d0f16adaf33e61b784e3a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a interrupt mode receive in slave mode.  <a href="#ga9808772192d0f16adaf33e61b784e3a3">More...</a><br/></td></tr>
<tr class="separator:ga9808772192d0f16adaf33e61b784e3a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">XI3c_SlaveSendPolled</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr, u16 ByteCount)</td></tr>
<tr class="memdesc:ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a polled mode send in slave mode.  <a href="#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">More...</a><br/></td></tr>
<tr class="separator:ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5999cb023a2ac9ca5dea7a9ed3edda5"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac5999cb023a2ac9ca5dea7a9ed3edda5">XI3c_SlaveRecvPolled</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr, u8 *MsgPtr)</td></tr>
<tr class="memdesc:gac5999cb023a2ac9ca5dea7a9ed3edda5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initiates a polled mode receive in slave mode.  <a href="#gac5999cb023a2ac9ca5dea7a9ed3edda5">More...</a><br/></td></tr>
<tr class="separator:gac5999cb023a2ac9ca5dea7a9ed3edda5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64fba1f66dc69a20b21f414cccb90752"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga64fba1f66dc69a20b21f414cccb90752">XI3c_SlaveInterruptHandler</a> (<a class="el" href="struct_x_i3c.html">XI3c</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga64fba1f66dc69a20b21f414cccb90752"><td class="mdescLeft">&#160;</td><td class="mdescRight">The interrupt handler for the slave mode.  <a href="#ga64fba1f66dc69a20b21f414cccb90752">More...</a><br/></td></tr>
<tr class="separator:ga64fba1f66dc69a20b21f414cccb90752"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:ga71e0cc721aa929d7f8e04206061d97c9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga71e0cc721aa929d7f8e04206061d97c9">XI3c_ConfigTable</a> []</td></tr>
<tr class="memdesc:ga71e0cc721aa929d7f8e04206061d97c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration table.  <a href="#ga71e0cc721aa929d7f8e04206061d97c9">More...</a><br/></td></tr>
<tr class="separator:ga71e0cc721aa929d7f8e04206061d97c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f1a8c5c110ac26b11c3c77fa1f39f57"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5f1a8c5c110ac26b11c3c77fa1f39f57">XI3c_ConfigTable</a> [XPAR_XI3C_NUM_INSTANCES]</td></tr>
<tr class="memdesc:ga5f1a8c5c110ac26b11c3c77fa1f39f57"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each I3C device in the system.  <a href="#ga5f1a8c5c110ac26b11c3c77fa1f39f57">More...</a><br/></td></tr>
<tr class="separator:ga5f1a8c5c110ac26b11c3c77fa1f39f57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa938ff976973faa16dd719be03700422"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa938ff976973faa16dd719be03700422">XI3C_VERSION_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gaa938ff976973faa16dd719be03700422"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register offsets for the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> device.  <a href="#gaa938ff976973faa16dd719be03700422">More...</a><br/></td></tr>
<tr class="separator:gaa938ff976973faa16dd719be03700422"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaeeafc8dc6cd85b8ecc8af8d545efa2d6">XI3C_RESET_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset Register.  <a href="#gaeeafc8dc6cd85b8ecc8af8d545efa2d6">More...</a><br/></td></tr>
<tr class="separator:gaeeafc8dc6cd85b8ecc8af8d545efa2d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5098e75930c837ad7cd5445535e4d283"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5098e75930c837ad7cd5445535e4d283">XI3C_CR_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga5098e75930c837ad7cd5445535e4d283"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="#ga5098e75930c837ad7cd5445535e4d283">More...</a><br/></td></tr>
<tr class="separator:ga5098e75930c837ad7cd5445535e4d283"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga201dee1806c408efbdf074cec11e02a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a>&#160;&#160;&#160;0x0C</td></tr>
<tr class="memdesc:ga201dee1806c408efbdf074cec11e02a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Address Register.  <a href="#ga201dee1806c408efbdf074cec11e02a1">More...</a><br/></td></tr>
<tr class="separator:ga201dee1806c408efbdf074cec11e02a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a3b3b24854197b7342e82f6d472ad60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga0a3b3b24854197b7342e82f6d472ad60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="#ga0a3b3b24854197b7342e82f6d472ad60">More...</a><br/></td></tr>
<tr class="separator:ga0a3b3b24854197b7342e82f6d472ad60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8db15484dd9ba5bbfcd041249b63ef4c">XI3C_INTR_STATUS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Register.  <a href="#ga8db15484dd9ba5bbfcd041249b63ef4c">More...</a><br/></td></tr>
<tr class="separator:ga8db15484dd9ba5bbfcd041249b63ef4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Enable(Rising Edge) Register.  <a href="#ga4eca8a991fb3151108c6933bfeb51c5e">More...</a><br/></td></tr>
<tr class="separator:ga4eca8a991fb3151108c6933bfeb51c5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga342ba5ba87f55302937c4b128f10f9da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:ga342ba5ba87f55302937c4b128f10f9da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Event Enable(Falling Edge) Register.  <a href="#ga342ba5ba87f55302937c4b128f10f9da">More...</a><br/></td></tr>
<tr class="separator:ga342ba5ba87f55302937c4b128f10f9da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga310ed8a56b21fca347c2cc0b3aa7f2f9">XI3C_CMD_FIFO_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Command FIFO Register.  <a href="#ga310ed8a56b21fca347c2cc0b3aa7f2f9">More...</a><br/></td></tr>
<tr class="separator:ga310ed8a56b21fca347c2cc0b3aa7f2f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38756ab021295465c1b621deb8d80ec2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga38756ab021295465c1b621deb8d80ec2">XI3C_WR_FIFO_OFFSET</a>&#160;&#160;&#160;0x24</td></tr>
<tr class="memdesc:ga38756ab021295465c1b621deb8d80ec2"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Write Data FIFO Register.  <a href="#ga38756ab021295465c1b621deb8d80ec2">More...</a><br/></td></tr>
<tr class="separator:ga38756ab021295465c1b621deb8d80ec2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c">XI3C_RD_FIFO_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Read Data FIFO Register.  <a href="#gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c">More...</a><br/></td></tr>
<tr class="separator:gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c063c7296db1c51db465c7e3609a8ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">XI3C_RESP_STATUS_FIFO_OFFSET</a>&#160;&#160;&#160;0x2C</td></tr>
<tr class="memdesc:ga2c063c7296db1c51db465c7e3609a8ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Response status FIFO Register.  <a href="#ga2c063c7296db1c51db465c7e3609a8ac">More...</a><br/></td></tr>
<tr class="separator:ga2c063c7296db1c51db465c7e3609a8ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d2708084fb73a3e790473dcd71a8b46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:ga2d2708084fb73a3e790473dcd71a8b46"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C CMD &amp; WR FIFO LVL Register.  <a href="#ga2d2708084fb73a3e790473dcd71a8b46">More...</a><br/></td></tr>
<tr class="separator:ga2d2708084fb73a3e790473dcd71a8b46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga699026be01649fea70621f96ab6f8dec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga699026be01649fea70621f96ab6f8dec"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C RESP &amp; RD FIFO LVL Register.  <a href="#ga699026be01649fea70621f96ab6f8dec">More...</a><br/></td></tr>
<tr class="separator:ga699026be01649fea70621f96ab6f8dec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19907a1f8fccab4045cec4f33a0a019b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga19907a1f8fccab4045cec4f33a0a019b"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SCL HIGH Register.  <a href="#ga19907a1f8fccab4045cec4f33a0a019b">More...</a><br/></td></tr>
<tr class="separator:ga19907a1f8fccab4045cec4f33a0a019b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacac5bc3663c87ed53678bbb88c58a737"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:gacac5bc3663c87ed53678bbb88c58a737"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SCL LOW Register.  <a href="#gacac5bc3663c87ed53678bbb88c58a737">More...</a><br/></td></tr>
<tr class="separator:gacac5bc3663c87ed53678bbb88c58a737"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a>&#160;&#160;&#160;0x40</td></tr>
<tr class="memdesc:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C SDA HOLD Register.  <a href="#gac98f0b52e9c9c40ccf5b41cd8fce94d6">More...</a><br/></td></tr>
<tr class="separator:gac98f0b52e9c9c40ccf5b41cd8fce94d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5eceedf78b84fdf70668668722c671af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a>&#160;&#160;&#160;0x44</td></tr>
<tr class="memdesc:ga5eceedf78b84fdf70668668722c671af"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C CONTROLLER BUS IDLE Register.  <a href="#ga5eceedf78b84fdf70668668722c671af">More...</a><br/></td></tr>
<tr class="separator:ga5eceedf78b84fdf70668668722c671af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad8bc7285bee2d4b07caf0be75751909"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a>&#160;&#160;&#160;0x48</td></tr>
<tr class="memdesc:gaad8bc7285bee2d4b07caf0be75751909"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C START SETUP Register.  <a href="#gaad8bc7285bee2d4b07caf0be75751909">More...</a><br/></td></tr>
<tr class="separator:gaad8bc7285bee2d4b07caf0be75751909"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b6019d7d90a6ffe16d5031c677da546"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a>&#160;&#160;&#160;0x4C</td></tr>
<tr class="memdesc:ga7b6019d7d90a6ffe16d5031c677da546"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C START HOLD Register.  <a href="#ga7b6019d7d90a6ffe16d5031c677da546">More...</a><br/></td></tr>
<tr class="separator:ga7b6019d7d90a6ffe16d5031c677da546"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9c766c72c30099de526c5d78a99ba5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:gaf9c766c72c30099de526c5d78a99ba5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C STOP Setup Register.  <a href="#gaf9c766c72c30099de526c5d78a99ba5c">More...</a><br/></td></tr>
<tr class="separator:gaf9c766c72c30099de526c5d78a99ba5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71c271412e577611810fe80fe0f51703"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga71c271412e577611810fe80fe0f51703"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C OD SCL HIGH Register.  <a href="#ga71c271412e577611810fe80fe0f51703">More...</a><br/></td></tr>
<tr class="separator:ga71c271412e577611810fe80fe0f51703"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C OD SCL LOW Register.  <a href="#ga5455e0616c1f4d0728b493ea0fb92b6f">More...</a><br/></td></tr>
<tr class="separator:ga5455e0616c1f4d0728b493ea0fb92b6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c64e1b8520dbdc358d94d36c3927256"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4c64e1b8520dbdc358d94d36c3927256">XI3C_TARGET_ADDR_BCR</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:ga4c64e1b8520dbdc358d94d36c3927256"><td class="mdescLeft">&#160;</td><td class="mdescRight">I3C Target dynamic Address and BCR Register.  <a href="#ga4c64e1b8520dbdc358d94d36c3927256">More...</a><br/></td></tr>
<tr class="separator:ga4c64e1b8520dbdc358d94d36c3927256"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga698dbf261cef62aea0e39e26e36444dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a>&#160;&#160;&#160;0x74</td></tr>
<tr class="memdesc:ga698dbf261cef62aea0e39e26e36444dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Write and Max Read length.  <a href="#ga698dbf261cef62aea0e39e26e36444dc">More...</a><br/></td></tr>
<tr class="separator:ga698dbf261cef62aea0e39e26e36444dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga211c542ff6c1ff32dbf288967d17d38a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga211c542ff6c1ff32dbf288967d17d38a">XI3C_EVENT</a>&#160;&#160;&#160;0x78</td></tr>
<tr class="memdesc:ga211c542ff6c1ff32dbf288967d17d38a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target events.  <a href="#ga211c542ff6c1ff32dbf288967d17d38a">More...</a><br/></td></tr>
<tr class="separator:ga211c542ff6c1ff32dbf288967d17d38a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab6f648bc7840eb8d61cb3c5d06d3f613">XI3C_GETMXDS</a>&#160;&#160;&#160;0x80</td></tr>
<tr class="memdesc:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Max Data Speed.  <a href="#gab6f648bc7840eb8d61cb3c5d06d3f613">More...</a><br/></td></tr>
<tr class="separator:gab6f648bc7840eb8d61cb3c5d06d3f613"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6da19b220a65d5ada6af1c9962d27184"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6da19b220a65d5ada6af1c9962d27184">XI3C_GETSTATUS</a>&#160;&#160;&#160;0x84</td></tr>
<tr class="memdesc:ga6da19b220a65d5ada6af1c9962d27184"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device current Status.  <a href="#ga6da19b220a65d5ada6af1c9962d27184">More...</a><br/></td></tr>
<tr class="separator:ga6da19b220a65d5ada6af1c9962d27184"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadeb959adfc801c98b78b2efa8fc09f8b">XI3C_GETCAPS_REG0</a>&#160;&#160;&#160;0x88</td></tr>
<tr class="memdesc:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Format 1 Capabilities.  <a href="#gadeb959adfc801c98b78b2efa8fc09f8b">More...</a><br/></td></tr>
<tr class="separator:gadeb959adfc801c98b78b2efa8fc09f8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">XI3C_GETCAPS_REG1</a>&#160;&#160;&#160;0x8c</td></tr>
<tr class="memdesc:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target Device Format 2 Capabilities.  <a href="#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">More...</a><br/></td></tr>
<tr class="separator:ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga459c04dba1fbcb734de88d489013acb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">XI3C_CON_RD_BYTE_COUNT</a>&#160;&#160;&#160;0x90</td></tr>
<tr class="memdesc:ga459c04dba1fbcb734de88d489013acb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read byte count register.  <a href="#ga459c04dba1fbcb734de88d489013acb6">More...</a><br/></td></tr>
<tr class="separator:ga459c04dba1fbcb734de88d489013acb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Version Register mask(s)</h2></td></tr>
<tr class="memitem:ga841758673758b882ccbf9d63d2989776"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga841758673758b882ccbf9d63d2989776">XI3C_INTERNAL_REVISION_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga841758673758b882ccbf9d63d2989776"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 3:0 - Internal revision.  <a href="#ga841758673758b882ccbf9d63d2989776">More...</a><br/></td></tr>
<tr class="separator:ga841758673758b882ccbf9d63d2989776"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d02cd501c9e204b141ff17882b0f78e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4d02cd501c9e204b141ff17882b0f78e">XI3C_CORE_PATCH_REVISION_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:ga4d02cd501c9e204b141ff17882b0f78e"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 7:4 - Patch revision.  <a href="#ga4d02cd501c9e204b141ff17882b0f78e">More...</a><br/></td></tr>
<tr class="separator:ga4d02cd501c9e204b141ff17882b0f78e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9a330fc6ac05e41f3e3c13b60ff74c8f">XI3C_CORE_REVISION_NUM_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 15:8 - Revision number.  <a href="#ga9a330fc6ac05e41f3e3c13b60ff74c8f">More...</a><br/></td></tr>
<tr class="separator:ga9a330fc6ac05e41f3e3c13b60ff74c8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffdb23d9d4f9825efe1089262b5084e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaffdb23d9d4f9825efe1089262b5084e3">XI3C_CORE_VERSION_MINOR_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gaffdb23d9d4f9825efe1089262b5084e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 23:16 - Minor version.  <a href="#gaffdb23d9d4f9825efe1089262b5084e3">More...</a><br/></td></tr>
<tr class="separator:gaffdb23d9d4f9825efe1089262b5084e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf3779fb2a8e036ac0bb9f80f7fd150c7">XI3C_CORE_VERSION_MAJOR_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BITS 31:24 - Major version.  <a href="#gaf3779fb2a8e036ac0bb9f80f7fd150c7">More...</a><br/></td></tr>
<tr class="separator:gaf3779fb2a8e036ac0bb9f80f7fd150c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaacd2bda9c2e5bd357c5fdee8ed2c8614">XI3C_CORE_REVISION_NUM_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="mdescLeft">&#160;</td><td class="mdescRight">Revision number shift.  <a href="#gaacd2bda9c2e5bd357c5fdee8ed2c8614">More...</a><br/></td></tr>
<tr class="separator:gaacd2bda9c2e5bd357c5fdee8ed2c8614"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Reset Register mask(s)</h2></td></tr>
<tr class="memitem:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1da2b90b0f8ce89043634891a7e9ba49">XI3C_SOFT_RESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Reset.  <a href="#ga1da2b90b0f8ce89043634891a7e9ba49">More...</a><br/></td></tr>
<tr class="separator:ga1da2b90b0f8ce89043634891a7e9ba49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0b5681e77e2c8502b4a0ae46df3a4b26">XI3C_CMD_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Cmd fifo reset.  <a href="#ga0b5681e77e2c8502b4a0ae46df3a4b26">More...</a><br/></td></tr>
<tr class="separator:ga0b5681e77e2c8502b4a0ae46df3a4b26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8813d9d73c5f1c95bc5867d60b829d6d">XI3C_WR_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Write fifo reset.  <a href="#ga8813d9d73c5f1c95bc5867d60b829d6d">More...</a><br/></td></tr>
<tr class="separator:ga8813d9d73c5f1c95bc5867d60b829d6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c07229c964da96edd30443b424def69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0c07229c964da96edd30443b424def69">XI3C_RD_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga0c07229c964da96edd30443b424def69"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Read fifo reset.  <a href="#ga0c07229c964da96edd30443b424def69">More...</a><br/></td></tr>
<tr class="separator:ga0c07229c964da96edd30443b424def69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacadbf79a1e643cce18a063a2289a1105"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacadbf79a1e643cce18a063a2289a1105">XI3C_RESP_FIFO_RESET_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gacadbf79a1e643cce18a063a2289a1105"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Response fifo reset.  <a href="#gacadbf79a1e643cce18a063a2289a1105">More...</a><br/></td></tr>
<tr class="separator:gacadbf79a1e643cce18a063a2289a1105"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac7a35f2e6a12487ef3dd2efa5e8f1992">XI3C_ALL_FIFOS_RESET_MASK</a>&#160;&#160;&#160;0x0000001E</td></tr>
<tr class="memdesc:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 to 4 - All fifos reset.  <a href="#gac7a35f2e6a12487ef3dd2efa5e8f1992">More...</a><br/></td></tr>
<tr class="separator:gac7a35f2e6a12487ef3dd2efa5e8f1992"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Control Register (CR) mask(s)</h2></td></tr>
<tr class="memitem:ga73562c3dd852ad953028edba3fc73184"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga73562c3dd852ad953028edba3fc73184">XI3C_CR_EN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga73562c3dd852ad953028edba3fc73184"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Core Enable.  <a href="#ga73562c3dd852ad953028edba3fc73184">More...</a><br/></td></tr>
<tr class="separator:ga73562c3dd852ad953028edba3fc73184"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaebe1db8ec816daf035299f26c0d3f98c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaebe1db8ec816daf035299f26c0d3f98c">XI3C_CR_ABORT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaebe1db8ec816daf035299f26c0d3f98c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Abort Transaction.  <a href="#gaebe1db8ec816daf035299f26c0d3f98c">More...</a><br/></td></tr>
<tr class="separator:gaebe1db8ec816daf035299f26c0d3f98c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4a05227ca83f5c2a8d5a3b2b5f2683ec">XI3C_CR_RESUME_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Resume Operation.  <a href="#ga4a05227ca83f5c2a8d5a3b2b5f2683ec">More...</a><br/></td></tr>
<tr class="separator:ga4a05227ca83f5c2a8d5a3b2b5f2683ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7aa5b9b25b40b6024fdd46c497a5761c">XI3C_CR_IBI_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - IBI Enable.  <a href="#ga7aa5b9b25b40b6024fdd46c497a5761c">More...</a><br/></td></tr>
<tr class="separator:ga7aa5b9b25b40b6024fdd46c497a5761c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26058f3049f96576501e4f6ca90de762"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga26058f3049f96576501e4f6ca90de762">XI3C_CR_HJ_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga26058f3049f96576501e4f6ca90de762"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Hot Join Enable.  <a href="#ga26058f3049f96576501e4f6ca90de762">More...</a><br/></td></tr>
<tr class="separator:ga26058f3049f96576501e4f6ca90de762"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6c6e38927f17536cb4cb8676d32c0d98">XI3C_CR_ACCEPT_CTRL_ROLE_REQ</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Generate ACK for secondary controller role request IBI.  <a href="#ga6c6e38927f17536cb4cb8676d32c0d98">More...</a><br/></td></tr>
<tr class="separator:ga6c6e38927f17536cb4cb8676d32c0d98"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Status Register (SR) mask(s)</h2></td></tr>
<tr class="memitem:ga07f073cf0ff84797b4d805541b4fbec7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga07f073cf0ff84797b4d805541b4fbec7">XI3C_SR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga07f073cf0ff84797b4d805541b4fbec7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="#ga07f073cf0ff84797b4d805541b4fbec7">More...</a><br/></td></tr>
<tr class="separator:ga07f073cf0ff84797b4d805541b4fbec7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59481855d3ba5232e103325915b8c9c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga59481855d3ba5232e103325915b8c9c9">XI3C_SR_CLK_STALL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga59481855d3ba5232e103325915b8c9c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="#ga59481855d3ba5232e103325915b8c9c9">More...</a><br/></td></tr>
<tr class="separator:ga59481855d3ba5232e103325915b8c9c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga734f3b7a052444daaed24d346b67cd43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga734f3b7a052444daaed24d346b67cd43">XI3C_SR_CMD_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga734f3b7a052444daaed24d346b67cd43"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="#ga734f3b7a052444daaed24d346b67cd43">More...</a><br/></td></tr>
<tr class="separator:ga734f3b7a052444daaed24d346b67cd43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3374e03a2587e874036d2f516a7de67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab3374e03a2587e874036d2f516a7de67">XI3C_SR_RESP_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gab3374e03a2587e874036d2f516a7de67"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="#gab3374e03a2587e874036d2f516a7de67">More...</a><br/></td></tr>
<tr class="separator:gab3374e03a2587e874036d2f516a7de67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9b9816a95d893384063e7fe2ce892ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">XI3C_SR_RESP_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gac9b9816a95d893384063e7fe2ce892ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="#gac9b9816a95d893384063e7fe2ce892ac">More...</a><br/></td></tr>
<tr class="separator:gac9b9816a95d893384063e7fe2ce892ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab8e7f9751ccb9a2bc60cbf3ef63ec5fe">XI3C_SR_WR_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="#gab8e7f9751ccb9a2bc60cbf3ef63ec5fe">More...</a><br/></td></tr>
<tr class="separator:gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabb62f870d6eaf9a0e84455a3b8f95802">XI3C_SR_RD_FULL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="#gabb62f870d6eaf9a0e84455a3b8f95802">More...</a><br/></td></tr>
<tr class="separator:gabb62f870d6eaf9a0e84455a3b8f95802"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga036ea1c62d3f28a118f5dcd137c128e2">XI3C_SR_IBI_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 7 - IBI.  <a href="#ga036ea1c62d3f28a118f5dcd137c128e2">More...</a><br/></td></tr>
<tr class="separator:ga036ea1c62d3f28a118f5dcd137c128e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6c4dfdb3896048df2fe69d50d72f081"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab6c4dfdb3896048df2fe69d50d72f081">XI3C_SR_HJ_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gab6c4dfdb3896048df2fe69d50d72f081"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 8 - Hot join.  <a href="#gab6c4dfdb3896048df2fe69d50d72f081">More...</a><br/></td></tr>
<tr class="separator:gab6c4dfdb3896048df2fe69d50d72f081"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga28fcad7bbd4d188d5f7115fc9a6c124a">XI3C_SR_CTRL_ROLE_REQUEST_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 9 - Received control role request.  <a href="#ga28fcad7bbd4d188d5f7115fc9a6c124a">More...</a><br/></td></tr>
<tr class="separator:ga28fcad7bbd4d188d5f7115fc9a6c124a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72bccabb2e243917849140d2fa491bd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga72bccabb2e243917849140d2fa491bd7">XI3C_SR_ERROR_TYPE_CE3_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga72bccabb2e243917849140d2fa491bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.  <a href="#ga72bccabb2e243917849140d2fa491bd7">More...</a><br/></td></tr>
<tr class="separator:ga72bccabb2e243917849140d2fa491bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79bae274f84eac816db1b3abc42aae5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga79bae274f84eac816db1b3abc42aae5c">XI3C_SR_RETURN_ROLE_REQ_ACK_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga79bae274f84eac816db1b3abc42aae5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 11 - Received ACK on controller role request back.  <a href="#ga79bae274f84eac816db1b3abc42aae5c">More...</a><br/></td></tr>
<tr class="separator:ga79bae274f84eac816db1b3abc42aae5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae32d0edcf3609f4aa31a8385861d6f00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae32d0edcf3609f4aa31a8385861d6f00">XI3C_SR_RD_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:gae32d0edcf3609f4aa31a8385861d6f00"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 12 - Read Fifo almost Full.  <a href="#gae32d0edcf3609f4aa31a8385861d6f00">More...</a><br/></td></tr>
<tr class="separator:gae32d0edcf3609f4aa31a8385861d6f00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga081fe15e4db5cd138cb5a79161530726"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga081fe15e4db5cd138cb5a79161530726">XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:ga081fe15e4db5cd138cb5a79161530726"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 13 - CMD FIFO empty.  <a href="#ga081fe15e4db5cd138cb5a79161530726">More...</a><br/></td></tr>
<tr class="separator:ga081fe15e4db5cd138cb5a79161530726"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaddc84e40ea7fbdede29fc1d687d31c82">XI3C_SR_WR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 14 - Write FIFO empty.  <a href="#gaddc84e40ea7fbdede29fc1d687d31c82">More...</a><br/></td></tr>
<tr class="separator:gaddc84e40ea7fbdede29fc1d687d31c82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga921e87b7a626211a1983b98dc3b22977"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga921e87b7a626211a1983b98dc3b22977"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 15 - Read FIFO empty.  <a href="#ga921e87b7a626211a1983b98dc3b22977">More...</a><br/></td></tr>
<tr class="separator:ga921e87b7a626211a1983b98dc3b22977"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7e4d65a8da33e49fda2aeba47497ab6a">XI3C_SR_SLV_DYNC_ADDR_DONE_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 19 - Dynamic address assigned to slave.  <a href="#ga7e4d65a8da33e49fda2aeba47497ab6a">More...</a><br/></td></tr>
<tr class="separator:ga7e4d65a8da33e49fda2aeba47497ab6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Status Register (SR) Shifts(s)</h2></td></tr>
<tr class="memitem:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga757f54fcb43fbdfe0ade99df244a68a7">XI3C_SR_BUS_BUSY_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="#ga757f54fcb43fbdfe0ade99df244a68a7">More...</a><br/></td></tr>
<tr class="separator:ga757f54fcb43fbdfe0ade99df244a68a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c649b5952826e117e67f92d4aee240a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6c649b5952826e117e67f92d4aee240a">XI3C_SR_CLK_STALL_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga6c649b5952826e117e67f92d4aee240a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="#ga6c649b5952826e117e67f92d4aee240a">More...</a><br/></td></tr>
<tr class="separator:ga6c649b5952826e117e67f92d4aee240a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1869fb29215628f67e0a0414eee54d0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga1869fb29215628f67e0a0414eee54d0e">XI3C_SR_CMD_FULL_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga1869fb29215628f67e0a0414eee54d0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="#ga1869fb29215628f67e0a0414eee54d0e">More...</a><br/></td></tr>
<tr class="separator:ga1869fb29215628f67e0a0414eee54d0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafdbb91c4f4f0bad0b9a1c43ff32d9d34">XI3C_SR_RESP_FULL_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="#gafdbb91c4f4f0bad0b9a1c43ff32d9d34">More...</a><br/></td></tr>
<tr class="separator:gafdbb91c4f4f0bad0b9a1c43ff32d9d34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga77ec3c78d800fc0a33781122c40fb8b8">XI3C_SR_RESP_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="#ga77ec3c78d800fc0a33781122c40fb8b8">More...</a><br/></td></tr>
<tr class="separator:ga77ec3c78d800fc0a33781122c40fb8b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9453d2e836832225cdb9166fbf2a509b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga9453d2e836832225cdb9166fbf2a509b">XI3C_SR_WR_FULL_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga9453d2e836832225cdb9166fbf2a509b"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="#ga9453d2e836832225cdb9166fbf2a509b">More...</a><br/></td></tr>
<tr class="separator:ga9453d2e836832225cdb9166fbf2a509b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5ab43aee70ecb74f43a04a2b4288c5ef">XI3C_SR_RD_FULL_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="#ga5ab43aee70ecb74f43a04a2b4288c5ef">More...</a><br/></td></tr>
<tr class="separator:ga5ab43aee70ecb74f43a04a2b4288c5ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga505303ab58a602428e0f9f4236c48b3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga505303ab58a602428e0f9f4236c48b3b">XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ga505303ab58a602428e0f9f4236c48b3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 19 - Dynamic address assigned to slave.  <a href="#ga505303ab58a602428e0f9f4236c48b3b">More...</a><br/></td></tr>
<tr class="separator:ga505303ab58a602428e0f9f4236c48b3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
response and other mask(s)</h2></td></tr>
<tr class="memitem:ga017f74b7be35475e374ccc4f8b9a5552"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga017f74b7be35475e374ccc4f8b9a5552"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_ID_MASK</b>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="separator:ga017f74b7be35475e374ccc4f8b9a5552"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac404bcf661ead5290c873291d0142765"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac404bcf661ead5290c873291d0142765"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_RW_MASK</b>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="separator:gac404bcf661ead5290c873291d0142765"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8befc05a5540da548a349678c621e78f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8befc05a5540da548a349678c621e78f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_CODE_MASK</b>&#160;&#160;&#160;0x000001E0</td></tr>
<tr class="separator:ga8befc05a5540da548a349678c621e78f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a6655dd9e46f36b9208cfce407b34ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8a6655dd9e46f36b9208cfce407b34ad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_BYTES_MASK</b>&#160;&#160;&#160;0x001FFE00</td></tr>
<tr class="separator:ga8a6655dd9e46f36b9208cfce407b34ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae2f7e3d67a606869e767cf5d05c0d8fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae2f7e3d67a606869e767cf5d05c0d8fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_CCC_MASK</b>&#160;&#160;&#160;0x1FE00000</td></tr>
<tr class="separator:gae2f7e3d67a606869e767cf5d05c0d8fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6de7f6e6bb570f4775dc76469f030062"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6de7f6e6bb570f4775dc76469f030062"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_7E_FRAME_MASK</b>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="separator:ga6de7f6e6bb570f4775dc76469f030062"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1938a386a2f3c813b05d2d4f6f211a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf1938a386a2f3c813b05d2d4f6f211a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MRL_MASK</b>&#160;&#160;&#160;0x0FFF0000</td></tr>
<tr class="separator:gaf1938a386a2f3c813b05d2d4f6f211a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa368f13aed4734e541d74056af2d4e52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa368f13aed4734e541d74056af2d4e52"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GRP_ADDR_MASK</b>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="separator:gaa368f13aed4734e541d74056af2d4e52"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
response and other shift(s)</h2></td></tr>
<tr class="memitem:gaa68362596244862289a0ecdecb713b24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa68362596244862289a0ecdecb713b24"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_TID_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:gaa68362596244862289a0ecdecb713b24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadde031c205995e6919531d6db852892b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadde031c205995e6919531d6db852892b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_RW_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:gadde031c205995e6919531d6db852892b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ded0321062d14b59702b9c84b8272ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ded0321062d14b59702b9c84b8272ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_CODE_SHIFT</b>&#160;&#160;&#160;5</td></tr>
<tr class="separator:ga1ded0321062d14b59702b9c84b8272ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2dd6bd969d456e60451062c88f1a7f06"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2dd6bd969d456e60451062c88f1a7f06"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_BYTES_SHIFT</b>&#160;&#160;&#160;9</td></tr>
<tr class="separator:ga2dd6bd969d456e60451062c88f1a7f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac09786b36a4c9097f223c4cc54f77227"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac09786b36a4c9097f223c4cc54f77227"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_RESP_LVL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gac09786b36a4c9097f223c4cc54f77227"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4c08a7a7b54c88b641328fb97eb72c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad4c08a7a7b54c88b641328fb97eb72c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_CCC_SHIFT</b>&#160;&#160;&#160;21</td></tr>
<tr class="separator:gad4c08a7a7b54c88b641328fb97eb72c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1f141082803c7b2b9bd1d98f9ec3e5e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae1f141082803c7b2b9bd1d98f9ec3e5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_SLV_RESP_7E_FRAME_SHIFT</b>&#160;&#160;&#160;29</td></tr>
<tr class="separator:gae1f141082803c7b2b9bd1d98f9ec3e5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb7531d55c7bbb07f52902688a0e1fbe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb7531d55c7bbb07f52902688a0e1fbe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CMD_LVL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gabb7531d55c7bbb07f52902688a0e1fbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ddc10a02fad8b842d5f0cd41d4c513a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ddc10a02fad8b842d5f0cd41d4c513a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MRL_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga7ddc10a02fad8b842d5f0cd41d4c513a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0789923e9c8a476df3377e1a2d0b981f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0789923e9c8a476df3377e1a2d0b981f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MWL_MRL_MSB_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:ga0789923e9c8a476df3377e1a2d0b981f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf55e388caa732df79e7dc38339548db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacf55e388caa732df79e7dc38339548db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GRP_ADDR_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:gacf55e388caa732df79e7dc38339548db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf900d5ea8aedc5cd5223081dc9f8b62"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacf900d5ea8aedc5cd5223081dc9f8b62"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GETSTATUS_FORMAT2_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gacf900d5ea8aedc5cd5223081dc9f8b62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57b26791795ff6191568fdeea15e217b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga57b26791795ff6191568fdeea15e217b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_GETMXDS_FORMAT3_DATA_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga57b26791795ff6191568fdeea15e217b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga507f769cc96f4e2e2419cd51479a5c83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga507f769cc96f4e2e2419cd51479a5c83"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS4_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:ga507f769cc96f4e2e2419cd51479a5c83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga157aa36ab6c5be15558175de9b6156fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga157aa36ab6c5be15558175de9b6156fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS3_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga157aa36ab6c5be15558175de9b6156fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fb63998f8659403b87b5c7681808136"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1fb63998f8659403b87b5c7681808136"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_CAPS2_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:ga1fb63998f8659403b87b5c7681808136"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
bit masks</h2></td></tr>
<tr class="memitem:ga4b47e1b9ddabc39f962e090ea2b3f91d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b47e1b9ddabc39f962e090ea2b3f91d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_1BIT_MASK</b>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:ga4b47e1b9ddabc39f962e090ea2b3f91d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga977ed3d17a2a8610bef6256aff7bcc67"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga977ed3d17a2a8610bef6256aff7bcc67"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_2BITS_MASK</b>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="separator:ga977ed3d17a2a8610bef6256aff7bcc67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e8331f0ba00e9258cef4d75d75c35d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9e8331f0ba00e9258cef4d75d75c35d2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_3BITS_MASK</b>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="separator:ga9e8331f0ba00e9258cef4d75d75c35d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd57e2db48d26315c7ad4bb8a1db66a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd57e2db48d26315c7ad4bb8a1db66a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_4BITS_MASK</b>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="separator:gacd57e2db48d26315c7ad4bb8a1db66a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga762f1005e1dfe41b4e449367e7c5c8c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga762f1005e1dfe41b4e449367e7c5c8c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_5BITS_MASK</b>&#160;&#160;&#160;0x0000001F</td></tr>
<tr class="separator:ga762f1005e1dfe41b4e449367e7c5c8c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga701ea9916070dd7d0aaa3f6e5e2a7820"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga701ea9916070dd7d0aaa3f6e5e2a7820"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_6BITS_MASK</b>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="separator:ga701ea9916070dd7d0aaa3f6e5e2a7820"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga285b0d4729f80a9936c1d09379be8dde"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga285b0d4729f80a9936c1d09379be8dde"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_7BITS_MASK</b>&#160;&#160;&#160;0x0000007F</td></tr>
<tr class="separator:ga285b0d4729f80a9936c1d09379be8dde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga397f53e4bcf6a6e3f4a824de8810c1be"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga397f53e4bcf6a6e3f4a824de8810c1be"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_8BITS_MASK</b>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="separator:ga397f53e4bcf6a6e3f4a824de8810c1be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf15b3eb130b00eb66d1d0ca0334f63a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf15b3eb130b00eb66d1d0ca0334f63a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_9BITS_MASK</b>&#160;&#160;&#160;0x000001FF</td></tr>
<tr class="separator:gaf15b3eb130b00eb66d1d0ca0334f63a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae081d7edf96c90780f710f900d5efa4c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae081d7edf96c90780f710f900d5efa4c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_10BITS_MASK</b>&#160;&#160;&#160;0x000003FF</td></tr>
<tr class="separator:gae081d7edf96c90780f710f900d5efa4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c1adf8c4596376fa193901e2a5a0e97"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3c1adf8c4596376fa193901e2a5a0e97"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_11BITS_MASK</b>&#160;&#160;&#160;0x000007FF</td></tr>
<tr class="separator:ga3c1adf8c4596376fa193901e2a5a0e97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga591d62fa59f55a741375c0842cdaf88f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga591d62fa59f55a741375c0842cdaf88f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_12BITS_MASK</b>&#160;&#160;&#160;0x00000FFF</td></tr>
<tr class="separator:ga591d62fa59f55a741375c0842cdaf88f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f4a0140ca1eac008af8323e830ad633"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f4a0140ca1eac008af8323e830ad633"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_13BITS_MASK</b>&#160;&#160;&#160;0x00001FFF</td></tr>
<tr class="separator:ga3f4a0140ca1eac008af8323e830ad633"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6c30a7d158b268f2f812eb2351274e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf6c30a7d158b268f2f812eb2351274e3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_14BITS_MASK</b>&#160;&#160;&#160;0x00003FFF</td></tr>
<tr class="separator:gaf6c30a7d158b268f2f812eb2351274e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga855ebd66800aeb296676452641e0dbef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga855ebd66800aeb296676452641e0dbef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_15BITS_MASK</b>&#160;&#160;&#160;0x00007FFF</td></tr>
<tr class="separator:ga855ebd66800aeb296676452641e0dbef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3751d8774e194f1f920499e944c68a6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3751d8774e194f1f920499e944c68a6a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_16BITS_MASK</b>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="separator:ga3751d8774e194f1f920499e944c68a6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb38bcb247a0389ea72d90d18171ccd3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb38bcb247a0389ea72d90d18171ccd3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_17BITS_MASK</b>&#160;&#160;&#160;0x0001FFFF</td></tr>
<tr class="separator:gabb38bcb247a0389ea72d90d18171ccd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ef00bea4092a3eb096d4de51b69c403"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ef00bea4092a3eb096d4de51b69c403"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_18BITS_MASK</b>&#160;&#160;&#160;0x0003FFFF</td></tr>
<tr class="separator:ga7ef00bea4092a3eb096d4de51b69c403"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6432fb32a8e65b5742747c198db8c7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad6432fb32a8e65b5742747c198db8c7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_19BITS_MASK</b>&#160;&#160;&#160;0x0007FFFF</td></tr>
<tr class="separator:gad6432fb32a8e65b5742747c198db8c7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac3ef8804e728831f2c39414bd0861679"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3ef8804e728831f2c39414bd0861679"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_20BITS_MASK</b>&#160;&#160;&#160;0x000FFFFF</td></tr>
<tr class="separator:gac3ef8804e728831f2c39414bd0861679"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae058d3e89399d015dd43473ab583c8b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae058d3e89399d015dd43473ab583c8b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MSB_8BITS_MASK</b>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="separator:gae058d3e89399d015dd43473ab583c8b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga236040697b992343689b1c23443bba9c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga236040697b992343689b1c23443bba9c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XI3C_MSB_16BITS_MASK</b>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="separator:ga236040697b992343689b1c23443bba9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
interrupt Register (INTR) mask(s)</h2></td></tr>
<tr class="memitem:gadde46b07ce0d970404a2fcf853661409"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gadde46b07ce0d970404a2fcf853661409">XI3C_INTR_BUS_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gadde46b07ce0d970404a2fcf853661409"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 0 - Bus Busy.  <a href="#gadde46b07ce0d970404a2fcf853661409">More...</a><br/></td></tr>
<tr class="separator:gadde46b07ce0d970404a2fcf853661409"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa09dbddd10e88620c2423f103d1bd4a0">XI3C_INTR_CLK_STALL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 1 - Clock Stall.  <a href="#gaa09dbddd10e88620c2423f103d1bd4a0">More...</a><br/></td></tr>
<tr class="separator:gaa09dbddd10e88620c2423f103d1bd4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10332d7b77429e9058fdcabe099cce36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga10332d7b77429e9058fdcabe099cce36">XI3C_INTR_CMD_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga10332d7b77429e9058fdcabe099cce36"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 2 - Cmd Fifo Full.  <a href="#ga10332d7b77429e9058fdcabe099cce36">More...</a><br/></td></tr>
<tr class="separator:ga10332d7b77429e9058fdcabe099cce36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga070c1bd5720ca64e0a76e8afa6d6b0a6">XI3C_INTR_RESP_FULL_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 3 - Resp Fifo Full.  <a href="#ga070c1bd5720ca64e0a76e8afa6d6b0a6">More...</a><br/></td></tr>
<tr class="separator:ga070c1bd5720ca64e0a76e8afa6d6b0a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabdb31954696a689f6a99d67ec180e6e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gabdb31954696a689f6a99d67ec180e6e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 4 - Resp Fifo not empty.  <a href="#gabdb31954696a689f6a99d67ec180e6e7">More...</a><br/></td></tr>
<tr class="separator:gabdb31954696a689f6a99d67ec180e6e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb00abdbc75747d0a18d1e8410d07a68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacb00abdbc75747d0a18d1e8410d07a68">XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gacb00abdbc75747d0a18d1e8410d07a68"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 5 - Write Fifo Full.  <a href="#gacb00abdbc75747d0a18d1e8410d07a68">More...</a><br/></td></tr>
<tr class="separator:gacb00abdbc75747d0a18d1e8410d07a68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0b74281de2f580f72138e92fa448244"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa0b74281de2f580f72138e92fa448244">XI3C_INTR_RD_FULL_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaa0b74281de2f580f72138e92fa448244"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 6 - Read Fifo Full.  <a href="#gaa0b74281de2f580f72138e92fa448244">More...</a><br/></td></tr>
<tr class="separator:gaa0b74281de2f580f72138e92fa448244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6015ecb529e10d7ac6c6d431144242d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a>&#160;&#160;&#160;0x0000007F</td></tr>
<tr class="memdesc:ga6015ecb529e10d7ac6c6d431144242d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">6:0 BITS  <a href="#ga6015ecb529e10d7ac6c6d431144242d1">More...</a><br/></td></tr>
<tr class="separator:ga6015ecb529e10d7ac6c6d431144242d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaddf7bc2cde2b99f5f00b09c8e39f9a73">XI3C_INTR_IBI_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 7 - IBI.  <a href="#gaddf7bc2cde2b99f5f00b09c8e39f9a73">More...</a><br/></td></tr>
<tr class="separator:gaddf7bc2cde2b99f5f00b09c8e39f9a73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0cc6f9c3c763acf9b012c571851dcf3a">XI3C_INTR_HJ_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 8 - Hot join.  <a href="#ga0cc6f9c3c763acf9b012c571851dcf3a">More...</a><br/></td></tr>
<tr class="separator:ga0cc6f9c3c763acf9b012c571851dcf3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga844df14294ccf0b9c2057b64e9be57ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga844df14294ccf0b9c2057b64e9be57ac">XI3C_INTR_CTRL_ROLE_REQUEST_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga844df14294ccf0b9c2057b64e9be57ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 9 - Received control role request.  <a href="#ga844df14294ccf0b9c2057b64e9be57ac">More...</a><br/></td></tr>
<tr class="separator:ga844df14294ccf0b9c2057b64e9be57ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69a1d41376d8e223e7d8468a50196b03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga69a1d41376d8e223e7d8468a50196b03">XI3C_INTR_ERROR_TYPE_CE3_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga69a1d41376d8e223e7d8468a50196b03"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role.  <a href="#ga69a1d41376d8e223e7d8468a50196b03">More...</a><br/></td></tr>
<tr class="separator:ga69a1d41376d8e223e7d8468a50196b03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga685b9e09fe59849441299b87aeaa1251"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga685b9e09fe59849441299b87aeaa1251">XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga685b9e09fe59849441299b87aeaa1251"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 11 - Received ACK on controller role request back.  <a href="#ga685b9e09fe59849441299b87aeaa1251">More...</a><br/></td></tr>
<tr class="separator:ga685b9e09fe59849441299b87aeaa1251"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga11f5367ba0a41f97993c47cff79ad7f4">XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 12 - Read Fifo almost Full.  <a href="#ga11f5367ba0a41f97993c47cff79ad7f4">More...</a><br/></td></tr>
<tr class="separator:ga11f5367ba0a41f97993c47cff79ad7f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf1c7c16b87d0571f53a041676f2c63a7">XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 13 - CMD FIFO empty.  <a href="#gaf1c7c16b87d0571f53a041676f2c63a7">More...</a><br/></td></tr>
<tr class="separator:gaf1c7c16b87d0571f53a041676f2c63a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf48010016e4266ae11f968791685435"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gacf48010016e4266ae11f968791685435">XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:gacf48010016e4266ae11f968791685435"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 14 - Write FIFO empty.  <a href="#gacf48010016e4266ae11f968791685435">More...</a><br/></td></tr>
<tr class="separator:gacf48010016e4266ae11f968791685435"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafb3daf54b287d6bde50bd16b2ce6b28d">XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="mdescLeft">&#160;</td><td class="mdescRight">BIT 15 - Read FIFO empty.  <a href="#gafb3daf54b287d6bde50bd16b2ce6b28d">More...</a><br/></td></tr>
<tr class="separator:gafb3daf54b287d6bde50bd16b2ce6b28d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab12a89030f0016bebe64fac8878cc57f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XI3c_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gab12a89030f0016bebe64fac8878cc57f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read an I3C register.  <a href="#gab12a89030f0016bebe64fac8878cc57f">More...</a><br/></td></tr>
<tr class="separator:gab12a89030f0016bebe64fac8878cc57f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td></tr>
<tr class="memdesc:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write an I3C register.  <a href="#ga6d1adc84977bc35bde5d82bb4a874d6b">More...</a><br/></td></tr>
<tr class="separator:ga6d1adc84977bc35bde5d82bb4a874d6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read WR FIFO LEVEL.  <a href="#ga0a979344e276171bf0bf87eb27c7ffd7">More...</a><br/></td></tr>
<tr class="separator:ga0a979344e276171bf0bf87eb27c7ffd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga5e01aa9fa4c727ed5fbd43736b05fad7">XI3c_CmdFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read CMD FIFO LEVEL.  <a href="#ga5e01aa9fa4c727ed5fbd43736b05fad7">More...</a><br/></td></tr>
<tr class="separator:ga5e01aa9fa4c727ed5fbd43736b05fad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">XI3c_RdFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read RD FIFO LEVEL.  <a href="#gac7ca28d237412cebb19bb2d5bde6eae6">More...</a><br/></td></tr>
<tr class="separator:gac7ca28d237412cebb19bb2d5bde6eae6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf68a808c2f04670d1b37a874ab0368dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaf68a808c2f04670d1b37a874ab0368dd">XI3c_RespFifoLevel</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf68a808c2f04670d1b37a874ab0368dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read RESP FIFO LEVEL.  <a href="#gaf68a808c2f04670d1b37a874ab0368dd">More...</a><br/></td></tr>
<tr class="separator:gaf68a808c2f04670d1b37a874ab0368dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga502dee04797d325155788141fa7db242"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga502dee04797d325155788141fa7db242">XI3c_RxFifoNotEmpty</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga502dee04797d325155788141fa7db242"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check Read FIFO empty status.  <a href="#ga502dee04797d325155788141fa7db242">More...</a><br/></td></tr>
<tr class="separator:ga502dee04797d325155788141fa7db242"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f">XI3c_RespFifoNotEmpty</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check Response FIFO empty status.  <a href="#ga0836e481b2a27d2f3b7f2992d7c1be0f">More...</a><br/></td></tr>
<tr class="separator:ga0836e481b2a27d2f3b7f2992d7c1be0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f2003a310655cbf699490aca1b1b460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga4f2003a310655cbf699490aca1b1b460"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Raising edge interrupts.  <a href="#ga4f2003a310655cbf699490aca1b1b460">More...</a><br/></td></tr>
<tr class="separator:ga4f2003a310655cbf699490aca1b1b460"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03622c20170a3203409c18ac0efcd1e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga03622c20170a3203409c18ac0efcd1e7">XI3c_EnableFEInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga03622c20170a3203409c18ac0efcd1e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Faling edge interrupts.  <a href="#ga03622c20170a3203409c18ac0efcd1e7">More...</a><br/></td></tr>
<tr class="separator:ga03622c20170a3203409c18ac0efcd1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaa44c7fcb3f5568047c20e274f1e0de37">XI3c_DisableREInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable raising edge interrupts.  <a href="#gaa44c7fcb3f5568047c20e274f1e0de37">More...</a><br/></td></tr>
<tr class="separator:gaa44c7fcb3f5568047c20e274f1e0de37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga6e84fcb954a3294f93ef7c65d74c22d8">XI3c_DisableFEInterrupts</a>(BaseAddress, IntrMask)</td></tr>
<tr class="memdesc:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable faling edge interrupts.  <a href="#ga6e84fcb954a3294f93ef7c65d74c22d8">More...</a><br/></td></tr>
<tr class="separator:ga6e84fcb954a3294f93ef7c65d74c22d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab22c206fca9f2352b27b6514e5076039"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab22c206fca9f2352b27b6514e5076039">XI3c_DisableAllREInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:gab22c206fca9f2352b27b6514e5076039"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all raising edge interrupts.  <a href="#gab22c206fca9f2352b27b6514e5076039">More...</a><br/></td></tr>
<tr class="separator:gab22c206fca9f2352b27b6514e5076039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a1f816187914a7db17f86e3a9570a04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0a1f816187914a7db17f86e3a9570a04">XI3c_DisableAllFEInterrupts</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga0a1f816187914a7db17f86e3a9570a04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable all faling edge interrupts.  <a href="#ga0a1f816187914a7db17f86e3a9570a04">More...</a><br/></td></tr>
<tr class="separator:ga0a1f816187914a7db17f86e3a9570a04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd">XI3c_FillSlaveSendCount</a>(InstancePtr, ByteCount)</td></tr>
<tr class="memdesc:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fill Slave send byte count value.  <a href="#ga2577bc2333d12a6bd75e2a79442f90bd">More...</a><br/></td></tr>
<tr class="separator:ga2577bc2333d12a6bd75e2a79442f90bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga93e2ff09fe04f9e588ca08ae03f9ae37">XI3c_ClearGrpAddr</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the group address of target.  <a href="#ga93e2ff09fe04f9e588ca08ae03f9ae37">More...</a><br/></td></tr>
<tr class="separator:ga93e2ff09fe04f9e588ca08ae03f9ae37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7acb6d781c60d402811ddc9f45552229"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7acb6d781c60d402811ddc9f45552229">XI3c_GetMWL</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga7acb6d781c60d402811ddc9f45552229"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Maximum write length.  <a href="#ga7acb6d781c60d402811ddc9f45552229">More...</a><br/></td></tr>
<tr class="separator:ga7acb6d781c60d402811ddc9f45552229"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab50db6a1880449022a970ccb4d8a6d25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25">XI3c_GetMRL</a>(InstancePtr)</td></tr>
<tr class="memdesc:gab50db6a1880449022a970ccb4d8a6d25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Maximum read length.  <a href="#gab50db6a1880449022a970ccb4d8a6d25">More...</a><br/></td></tr>
<tr class="separator:gab50db6a1880449022a970ccb4d8a6d25"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga199da98d8ddcd495482b436d294ec75d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIMEOUT_COUNTER&#160;&#160;&#160;2000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Wait for 2 sec in worst case. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="ga201dee1806c408efbdf074cec11e02a1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_ADDRESS_OFFSET&#160;&#160;&#160;0x0C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target Address Register. </p>

</div>
</div>
<a class="anchor" id="gac7a35f2e6a12487ef3dd2efa5e8f1992"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_ALL_FIFOS_RESET_MASK&#160;&#160;&#160;0x0000001E</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 to 4 - All fifos reset. </p>

</div>
</div>
<a class="anchor" id="ga6015ecb529e10d7ac6c6d431144242d1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_ALL_INTR_MASK&#160;&#160;&#160;0x0000007F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>6:0 BITS </p>

</div>
</div>
<a class="anchor" id="ga1cd52261485c5865d5b0ff1fc16e9fa9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_BASEADDR&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AXI_I3C0 Base Address #define XI3C_BASEADDR 0x80000000. </p>

</div>
</div>
<a class="anchor" id="ga5eceedf78b84fdf70668668722c671af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_BUS_IDLE_OFFSET&#160;&#160;&#160;0x44</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C CONTROLLER BUS IDLE Register. </p>

</div>
</div>
<a class="anchor" id="gab00798fa6acd361fcd8c15ef50065bde"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_BusIsBusy</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td>&#160;&#160;&#160;(<a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>((BaseAddress), <a class="el" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>) &amp; <a class="el" href="group___overview.html#ga07f073cf0ff84797b4d805541b4fbec7">XI3C_SR_BUS_BUSY_MASK</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Checks whether the I3C bus is busy. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: s32 <a class="el" href="group___overview.html#gab00798fa6acd361fcd8c15ef50065bde" title="Checks whether the I3C bus is busy. ">XI3c_BusIsBusy(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga93e2ff09fe04f9e588ca08ae03f9ae37"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_ClearGrpAddr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>),                      \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a>,                                    \</div>
<div class="line">                      ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,         \</div>
<div class="line">                                     <a class="code" href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a>))                    \</div>
<div class="line">                      &amp; (~XI3C_GRP_ADDR_MASK)))</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga201dee1806c408efbdf074cec11e02a1"><div class="ttname"><a href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a></div><div class="ttdeci">#define XI3C_ADDRESS_OFFSET</div><div class="ttdoc">Target Address Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:60</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Clear the group address of target. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">Byte</td><td>count value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd" title="Fill Slave send byte count value. ">XI3c_FillSlaveSendCount(XI3c *InstancePtr, u16 ByteCount)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga310ed8a56b21fca347c2cc0b3aa7f2f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CMD_FIFO_OFFSET&#160;&#160;&#160;0x20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C Command FIFO Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga0b5681e77e2c8502b4a0ae46df3a4b26"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CMD_FIFO_RESET_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 - Cmd fifo reset. </p>

</div>
</div>
<a class="anchor" id="ga5e01aa9fa4c727ed5fbd43736b05fad7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_CmdFifoLevel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,            \</div>
<div class="line">                            <a class="code" href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a>) &amp;              \</div>
<div class="line">              XI3C_MSB_16BITS_MASK) &gt;&gt; XI3C_CMD_LVL_SHIFT)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga2d2708084fb73a3e790473dcd71a8b46"><div class="ttname"><a href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a></div><div class="ttdeci">#define XI3C_FIFO_LVL_STATUS_OFFSET</div><div class="ttdoc">I3C CMD &amp;amp; WR FIFO LVL Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:69</div></div>
</div><!-- fragment -->
<p>Read CMD FIFO LEVEL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga5e01aa9fa4c727ed5fbd43736b05fad7" title="Read CMD FIFO LEVEL. ">XI3c_CmdFifoLevel(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga459c04dba1fbcb734de88d489013acb6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CON_RD_BYTE_COUNT&#160;&#160;&#160;0x90</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read byte count register. </p>

</div>
</div>
<a class="anchor" id="ga4d02cd501c9e204b141ff17882b0f78e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CORE_PATCH_REVISION_MASK&#160;&#160;&#160;0x000000F0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BITS 7:4 - Patch revision. </p>

</div>
</div>
<a class="anchor" id="ga9a330fc6ac05e41f3e3c13b60ff74c8f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CORE_REVISION_NUM_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BITS 15:8 - Revision number. </p>

</div>
</div>
<a class="anchor" id="gaacd2bda9c2e5bd357c5fdee8ed2c8614"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CORE_REVISION_NUM_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Revision number shift. </p>

</div>
</div>
<a class="anchor" id="gaf3779fb2a8e036ac0bb9f80f7fd150c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CORE_VERSION_MAJOR_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BITS 31:24 - Major version. </p>

</div>
</div>
<a class="anchor" id="gaffdb23d9d4f9825efe1089262b5084e3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CORE_VERSION_MINOR_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BITS 23:16 - Minor version. </p>

</div>
</div>
<a class="anchor" id="gaebe1db8ec816daf035299f26c0d3f98c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_ABORT_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 - Abort Transaction. </p>

</div>
</div>
<a class="anchor" id="ga6c6e38927f17536cb4cb8676d32c0d98"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_ACCEPT_CTRL_ROLE_REQ&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 5 - Generate ACK for secondary controller role request IBI. </p>

</div>
</div>
<a class="anchor" id="ga73562c3dd852ad953028edba3fc73184"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_EN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 0 - Core Enable. </p>

</div>
</div>
<a class="anchor" id="ga26058f3049f96576501e4f6ca90de762"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_HJ_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 4 - Hot Join Enable. </p>

</div>
</div>
<a class="anchor" id="ga7aa5b9b25b40b6024fdd46c497a5761c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_IBI_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 3 - IBI Enable. </p>

</div>
</div>
<a class="anchor" id="ga5098e75930c837ad7cd5445535e4d283"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_OFFSET&#160;&#160;&#160;0x08</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control Register. </p>

</div>
</div>
<a class="anchor" id="ga4a05227ca83f5c2a8d5a3b2b5f2683ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_CR_RESUME_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 2 - Resume Operation. </p>

</div>
</div>
<a class="anchor" id="ga0a1f816187914a7db17f86e3a9570a04"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_DisableAllFEInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>,               \</div>
<div class="line">                      ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress,<a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>))  \</div>
<div class="line">                      &amp; ~(<a class="code" href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a>)))                         \</div>
<div class="ttc" id="group___overview_html_ga6015ecb529e10d7ac6c6d431144242d1"><div class="ttname"><a href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a></div><div class="ttdeci">#define XI3C_ALL_INTR_MASK</div><div class="ttdoc">6:0 BITS </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:245</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga342ba5ba87f55302937c4b128f10f9da"><div class="ttname"><a href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_FE_OFFSET</div><div class="ttdoc">Status Event Enable(Falling Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:64</div></div>
</div><!-- fragment -->
<p>Disable all faling edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga0a1f816187914a7db17f86e3a9570a04" title="Disable all faling edge interrupts. ">XI3c_DisableAllFEInterrupts(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gab22c206fca9f2352b27b6514e5076039"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_DisableAllREInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>,               \</div>
<div class="line">                      ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress,<a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>))  \</div>
<div class="line">                      &amp; ~(<a class="code" href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a>)))                         \</div>
<div class="ttc" id="group___overview_html_ga6015ecb529e10d7ac6c6d431144242d1"><div class="ttname"><a href="group___overview.html#ga6015ecb529e10d7ac6c6d431144242d1">XI3C_ALL_INTR_MASK</a></div><div class="ttdeci">#define XI3C_ALL_INTR_MASK</div><div class="ttdoc">6:0 BITS </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:245</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga4eca8a991fb3151108c6933bfeb51c5e"><div class="ttname"><a href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_RE_OFFSET</div><div class="ttdoc">Status Event Enable(Rising Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:63</div></div>
</div><!-- fragment -->
<p>Disable all raising edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#gab22c206fca9f2352b27b6514e5076039" title="Disable all raising edge interrupts. ">XI3c_DisableAllREInterrupts(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga6e84fcb954a3294f93ef7c65d74c22d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_DisableFEInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">IntrMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>,               \</div>
<div class="line">                      ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress,<a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>))  \</div>
<div class="line">                      &amp; ~(IntrMask)))                                   \</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga342ba5ba87f55302937c4b128f10f9da"><div class="ttname"><a href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_FE_OFFSET</div><div class="ttdoc">Status Event Enable(Falling Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:64</div></div>
</div><!-- fragment -->
<p>Disable faling edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga6e84fcb954a3294f93ef7c65d74c22d8" title="Disable faling edge interrupts. ">XI3c_DisableFEInterrupts(XI3c *InstancePtr, u32 IntrMask)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gaa44c7fcb3f5568047c20e274f1e0de37"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_DisableREInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">IntrMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>,               \</div>
<div class="line">                      ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress,<a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>))  \</div>
<div class="line">                      &amp; ~(IntrMask)))                                   \</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga4eca8a991fb3151108c6933bfeb51c5e"><div class="ttname"><a href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_RE_OFFSET</div><div class="ttdoc">Status Event Enable(Rising Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:63</div></div>
</div><!-- fragment -->
<p>Disable raising edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#gaa44c7fcb3f5568047c20e274f1e0de37" title="Disable raising edge interrupts. ">XI3c_DisableREInterrupts(XI3c *InstancePtr, u32 IntrMask)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga03622c20170a3203409c18ac0efcd1e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_EnableFEInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">IntrMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>,                   \</div>
<div class="line">                        ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a>)) | \</div>
<div class="line">                        (IntrMask)))</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga342ba5ba87f55302937c4b128f10f9da"><div class="ttname"><a href="group___overview.html#ga342ba5ba87f55302937c4b128f10f9da">XI3C_INTR_FE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_FE_OFFSET</div><div class="ttdoc">Status Event Enable(Falling Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:64</div></div>
</div><!-- fragment -->
<p>Enable Faling edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga03622c20170a3203409c18ac0efcd1e7" title="Enable Faling edge interrupts. ">XI3c_EnableFEInterrupts(XI3c *InstancePtr, u32 IntrMask)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>.</p>

</div>
</div>
<a class="anchor" id="ga4f2003a310655cbf699490aca1b1b460"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_EnableREInterrupts</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">IntrMask&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((BaseAddress), <a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>,                   \</div>
<div class="line">                        ((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(BaseAddress, <a class="code" href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a>)) | \</div>
<div class="line">                        (IntrMask)))</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga4eca8a991fb3151108c6933bfeb51c5e"><div class="ttname"><a href="group___overview.html#ga4eca8a991fb3151108c6933bfeb51c5e">XI3C_INTR_RE_OFFSET</a></div><div class="ttdeci">#define XI3C_INTR_RE_OFFSET</div><div class="ttdoc">Status Event Enable(Rising Edge) Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:63</div></div>
</div><!-- fragment -->
<p>Enable Raising edge interrupts. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Base</td><td>address of the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">interrupt</td><td>mask value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460" title="Enable Raising edge interrupts. ">XI3c_EnableREInterrupts(XI3c *InstancePtr, u32 IntrMask)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>, <a class="el" href="group___overview.html#gae0d7f9bd9e10d5de348154d823d7bea0">XI3c_IbiRecv()</a>, <a class="el" href="group___overview.html#ga65bbec96638b9e2f5627452ac9a9ae48">XI3c_MasterRecv()</a>, and <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>.</p>

</div>
</div>
<a class="anchor" id="ga211c542ff6c1ff32dbf288967d17d38a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_EVENT&#160;&#160;&#160;0x78</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target events. </p>

</div>
</div>
<a class="anchor" id="ga699026be01649fea70621f96ab6f8dec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_FIFO_LVL_STATUS_1_OFFSET&#160;&#160;&#160;0x34</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C RESP &amp; RD FIFO LVL Register. </p>

</div>
</div>
<a class="anchor" id="ga2d2708084fb73a3e790473dcd71a8b46"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_FIFO_LVL_STATUS_OFFSET&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C CMD &amp; WR FIFO LVL Register. </p>

</div>
</div>
<a class="anchor" id="ga2577bc2333d12a6bd75e2a79442f90bd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_FillSlaveSendCount</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">ByteCount&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>((InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>),                      \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">XI3C_CON_RD_BYTE_COUNT</a>,                                 \</div>
<div class="line">                      (((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,        \</div>
<div class="line">                                      <a class="code" href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">XI3C_CON_RD_BYTE_COUNT</a>))                \</div>
<div class="line">                      &amp; (~XI3C_16BITS_MASK)) | (ByteCount &amp; XI3C_16BITS_MASK)))</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga459c04dba1fbcb734de88d489013acb6"><div class="ttname"><a href="group___overview.html#ga459c04dba1fbcb734de88d489013acb6">XI3C_CON_RD_BYTE_COUNT</a></div><div class="ttdeci">#define XI3C_CON_RD_BYTE_COUNT</div><div class="ttdoc">Read byte count register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:87</div></div>
</div><!-- fragment -->
<p>Fill Slave send byte count value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance. </td></tr>
    <tr><td class="paramname">Byte</td><td>count value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd" title="Fill Slave send byte count value. ">XI3c_FillSlaveSendCount(XI3c *InstancePtr, u16 ByteCount)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga28021172cfe5d1d3dfb20e8f3f58c94f">XI3c_SlaveSend()</a>, and <a class="el" href="group___overview.html#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">XI3c_SlaveSendPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf139462f725a3c0b3a8a3cedfa204898"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetBusIdleTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                 \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga5eceedf78b84fdf70668668722c671af"><div class="ttname"><a href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a></div><div class="ttdeci">#define XI3C_BUS_IDLE_OFFSET</div><div class="ttdoc">I3C CONTROLLER BUS IDLE Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:74</div></div>
</div><!-- fragment -->
<p>Gets bus idle time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gaf139462f725a3c0b3a8a3cedfa204898" title="Gets bus idle time of I3C. ">XI3c_GetBusIdleTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gadeb959adfc801c98b78b2efa8fc09f8b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_GETCAPS_REG0&#160;&#160;&#160;0x88</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target Device Format 1 Capabilities. </p>

</div>
</div>
<a class="anchor" id="ga3a5ef5be5a8d1b70ce3fb3da4620c04f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_GETCAPS_REG1&#160;&#160;&#160;0x8c</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target Device Format 2 Capabilities. </p>

</div>
</div>
<a class="anchor" id="ga081b8df5809a3e6efc26ac7fe120c90b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetDynaAddr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>((InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>), <a class="code" href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a>)\</div>
<div class="line">         &amp; XI3C_8BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga201dee1806c408efbdf074cec11e02a1"><div class="ttname"><a href="group___overview.html#ga201dee1806c408efbdf074cec11e02a1">XI3C_ADDRESS_OFFSET</a></div><div class="ttdeci">#define XI3C_ADDRESS_OFFSET</div><div class="ttdoc">Target Address Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:60</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets the dynamic address of the I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The address returned includes parity. C-style signature: u8 <a class="el" href="group___overview.html#ga081b8df5809a3e6efc26ac7fe120c90b" title="Gets the dynamic address of the I3C. ">XI3c_GetDynaAddr(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga7029965ea1ab665e22bd199cefd9e2a4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetErrorStatus</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((<a class="code" href="group___overview.html#gaf2a15d20998f93c82b2ea5803a407d8c">XI3c_GetResponseData</a>(InstancePtr)) &amp; XI3C_RESP_CODE_MASK)            \</div>
<div class="line">                                &gt;&gt; XI3C_RESP_CODE_SHIFT)</div>
<div class="ttc" id="group___overview_html_gaf2a15d20998f93c82b2ea5803a407d8c"><div class="ttname"><a href="group___overview.html#gaf2a15d20998f93c82b2ea5803a407d8c">XI3c_GetResponseData</a></div><div class="ttdeci">#define XI3c_GetResponseData(InstancePtr)</div><div class="ttdoc">Gets Response data of I3C. </div><div class="ttdef"><b>Definition:</b> xi3c.h:553</div></div>
</div><!-- fragment -->
<p>Gets error status from response of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 if no error. error code if any error.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga7029965ea1ab665e22bd199cefd9e2a4" title="Gets error status from response of I3C. ">XI3c_GetErrorStatus(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="gab50db6a1880449022a970ccb4d8a6d25"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetMRL</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,            \</div>
<div class="line">                           <a class="code" href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a>) &gt;&gt; XI3C_MRL_SHIFT) &amp;           \</div>
<div class="line">                           XI3C_12BITS_MASK)</div>
<div class="ttc" id="group___overview_html_ga698dbf261cef62aea0e39e26e36444dc"><div class="ttname"><a href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a></div><div class="ttdeci">#define XI3C_MWL_MRL</div><div class="ttdoc">Maximum Write and Max Read length. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:81</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Read Maximum read length. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Maximum read length.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25" title="Read Maximum read length. ">XI3c_GetMRL(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga28021172cfe5d1d3dfb20e8f3f58c94f">XI3c_SlaveSend()</a>, and <a class="el" href="group___overview.html#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">XI3c_SlaveSendPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7acb6d781c60d402811ddc9f45552229"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetMWL</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,             \</div>
<div class="line">                           <a class="code" href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a>) &amp;                              \</div>
<div class="line">                           XI3C_12BITS_MASK)</div>
<div class="ttc" id="group___overview_html_ga698dbf261cef62aea0e39e26e36444dc"><div class="ttname"><a href="group___overview.html#ga698dbf261cef62aea0e39e26e36444dc">XI3C_MWL_MRL</a></div><div class="ttdeci">#define XI3C_MWL_MRL</div><div class="ttdoc">Maximum Write and Max Read length. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:81</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Read Maximum write length. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Maximum write length.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#ga7acb6d781c60d402811ddc9f45552229" title="Read Maximum write length. ">XI3c_GetMWL(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gab6f648bc7840eb8d61cb3c5d06d3f613"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_GETMXDS&#160;&#160;&#160;0x80</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target Device Max Data Speed. </p>

</div>
</div>
<a class="anchor" id="gaf2a15d20998f93c82b2ea5803a407d8c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetResponseData</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                           \</div>
<div class="line">                     <a class="code" href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">XI3C_RESP_STATUS_FIFO_OFFSET</a>)</div>
<div class="ttc" id="group___overview_html_ga2c063c7296db1c51db465c7e3609a8ac"><div class="ttname"><a href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">XI3C_RESP_STATUS_FIFO_OFFSET</a></div><div class="ttdeci">#define XI3C_RESP_STATUS_FIFO_OFFSET</div><div class="ttdoc">I3C Response status FIFO Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:68</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets Response data of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Response value.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gaf2a15d20998f93c82b2ea5803a407d8c" title="Gets Response data of I3C. ">XI3c_GetResponseData(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga34208c49e1fb181e5d75006a27cee535"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetRevisionNumber</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                        \</div>
<div class="line">                       <a class="code" href="group___overview.html#gaa938ff976973faa16dd719be03700422">XI3C_VERSION_OFFSET</a>)) &amp; <a class="code" href="group___overview.html#ga9a330fc6ac05e41f3e3c13b60ff74c8f">XI3C_CORE_REVISION_NUM_MASK</a>)     \</div>
<div class="line">                       &gt;&gt; <a class="code" href="group___overview.html#gaacd2bda9c2e5bd357c5fdee8ed2c8614">XI3C_CORE_REVISION_NUM_SHIFT</a>)</div>
<div class="ttc" id="group___overview_html_gaacd2bda9c2e5bd357c5fdee8ed2c8614"><div class="ttname"><a href="group___overview.html#gaacd2bda9c2e5bd357c5fdee8ed2c8614">XI3C_CORE_REVISION_NUM_SHIFT</a></div><div class="ttdeci">#define XI3C_CORE_REVISION_NUM_SHIFT</div><div class="ttdoc">Revision number shift. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:102</div></div>
<div class="ttc" id="group___overview_html_ga9a330fc6ac05e41f3e3c13b60ff74c8f"><div class="ttname"><a href="group___overview.html#ga9a330fc6ac05e41f3e3c13b60ff74c8f">XI3C_CORE_REVISION_NUM_MASK</a></div><div class="ttdeci">#define XI3C_CORE_REVISION_NUM_MASK</div><div class="ttdoc">BITS 15:8 - Revision number. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:98</div></div>
<div class="ttc" id="group___overview_html_gaa938ff976973faa16dd719be03700422"><div class="ttname"><a href="group___overview.html#gaa938ff976973faa16dd719be03700422">XI3C_VERSION_OFFSET</a></div><div class="ttdeci">#define XI3C_VERSION_OFFSET</div><div class="ttdoc">Register offsets for the XI3c device. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:57</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets Core Revision number of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga34208c49e1fb181e5d75006a27cee535" title="Gets Core Revision number of I3C. ">XI3c_GetRevisionNumber(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf4c3c52633de88fa131ad59aef0870a9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetSclHighTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                      \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga19907a1f8fccab4045cec4f33a0a019b"><div class="ttname"><a href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SCL_HIGH_TIME_OFFSET</div><div class="ttdoc">I3C SCL HIGH Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:71</div></div>
</div><!-- fragment -->
<p>Gets scl high time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gaf4c3c52633de88fa131ad59aef0870a9" title="Gets scl high time of I3C. ">XI3c_GetSclHighTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga761aaa270ed25b3c92f7f9212ba947ea"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetSclLowTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                     \</div>
<div class="line">                       <a class="code" href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gacac5bc3663c87ed53678bbb88c58a737"><div class="ttname"><a href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SCL_LOW_TIME_OFFSET</div><div class="ttdoc">I3C SCL LOW Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:72</div></div>
</div><!-- fragment -->
<p>Gets scl low time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga761aaa270ed25b3c92f7f9212ba947ea" title="Gets scl low time of I3C. ">XI3c_GetSclLowTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga09c6e2c3a3d2a2af74cbe60aae6d8e0a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetSclOdHighTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_ga71c271412e577611810fe80fe0f51703"><div class="ttname"><a href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_OD_SCL_HIGH_TIME_OFFSET</div><div class="ttdoc">I3C OD SCL HIGH Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:78</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets Scl open drain high time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga09c6e2c3a3d2a2af74cbe60aae6d8e0a" title="Gets Scl open drain high time of I3C. ">XI3c_GetSclOdHighTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gac1e4d1386198f402fa21ad9c36ea60f2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetSclOdLowTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                 \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_ga5455e0616c1f4d0728b493ea0fb92b6f"><div class="ttname"><a href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_OD_SCL_LOW_TIME_OFFSET</div><div class="ttdoc">I3C OD SCL LOW Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:79</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets Scl open drain low time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gac1e4d1386198f402fa21ad9c36ea60f2" title="Gets Scl open drain low time of I3C. ">XI3c_GetSclOdLowTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga00bd308ab29e0112b613fa5001366a2c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetSdaHoldTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                      \</div>
<div class="line">                       <a class="code" href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gac98f0b52e9c9c40ccf5b41cd8fce94d6"><div class="ttname"><a href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SDA_HOLD_TIME_OFFSET</div><div class="ttdoc">I3C SDA HOLD Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:73</div></div>
</div><!-- fragment -->
<p>Gets sda hold time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga00bd308ab29e0112b613fa5001366a2c" title="Gets sda hold time of I3C. ">XI3c_GetSdaHoldTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga6da19b220a65d5ada6af1c9962d27184"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_GETSTATUS&#160;&#160;&#160;0x84</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Target Device current Status. </p>

</div>
</div>
<a class="anchor" id="ga3e759c8db730bde42150bee0ad9f423a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetThdStartTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                 \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga7b6019d7d90a6ffe16d5031c677da546"><div class="ttname"><a href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a></div><div class="ttdeci">#define XI3C_THD_START_OFFSET</div><div class="ttdoc">I3C START HOLD Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:76</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>This function gets Thd Start time. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga3e759c8db730bde42150bee0ad9f423a" title="This function gets Thd Start time. ">XI3c_GetThdStartTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gacbf0a51b190414a36c9d1407cdbfb53e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetTsuStartTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                       <a class="code" href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gaad8bc7285bee2d4b07caf0be75751909"><div class="ttname"><a href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a></div><div class="ttdeci">#define XI3C_TSU_START_OFFSET</div><div class="ttdoc">I3C START SETUP Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:75</div></div>
</div><!-- fragment -->
<p>Gets Tsu Start time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gacbf0a51b190414a36c9d1407cdbfb53e" title="Gets Tsu Start time of I3C. ">XI3c_GetTsuStartTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gacf75ae078e7f9fc0d9ba22c01a5636b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_GetTsuStopTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                 \</div>
<div class="line">                       <a class="code" href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a>)) &amp; XI3C_18BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_gaf9c766c72c30099de526c5d78a99ba5c"><div class="ttname"><a href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a></div><div class="ttdeci">#define XI3C_TSU_STOP_OFFSET</div><div class="ttdoc">I3C STOP Setup Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:77</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Gets Tsu Stop time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gacf75ae078e7f9fc0d9ba22c01a5636b2" title="Gets Tsu Stop time of I3C. ">XI3c_GetTsuStopTime(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga274b0856bce55f704b8ad00e939d8898"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_H</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>by using protection macros </p>

</div>
</div>
<a class="anchor" id="ga3f42f6b73f1536013fce8bef9a8b089c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; prevent circular inclusions </p>
<p>by using protection macros </p>

</div>
</div>
<a class="anchor" id="ga841758673758b882ccbf9d63d2989776"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTERNAL_REVISION_MASK&#160;&#160;&#160;0x0000000F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BITS 3:0 - Internal revision. </p>

</div>
</div>
<a class="anchor" id="gadde46b07ce0d970404a2fcf853661409"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_BUS_BUSY_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 0 - Bus Busy. </p>

</div>
</div>
<a class="anchor" id="gaa09dbddd10e88620c2423f103d1bd4a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_CLK_STALL_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 - Clock Stall. </p>

</div>
</div>
<a class="anchor" id="gaf1c7c16b87d0571f53a041676f2c63a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_CMD_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00002000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 13 - CMD FIFO empty. </p>

</div>
</div>
<a class="anchor" id="ga10332d7b77429e9058fdcabe099cce36"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_CMD_FULL_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 2 - Cmd Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga844df14294ccf0b9c2057b64e9be57ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_CTRL_ROLE_REQUEST_MASK&#160;&#160;&#160;0x00000200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 9 - Received control role request. </p>

</div>
</div>
<a class="anchor" id="ga69a1d41376d8e223e7d8468a50196b03"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_ERROR_TYPE_CE3_MASK&#160;&#160;&#160;0x00000400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. </p>

</div>
</div>
<a class="anchor" id="ga342ba5ba87f55302937c4b128f10f9da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_FE_OFFSET&#160;&#160;&#160;0x1C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Status Event Enable(Falling Edge) Register. </p>

</div>
</div>
<a class="anchor" id="ga0cc6f9c3c763acf9b012c571851dcf3a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_HJ_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 8 - Hot join. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>, and <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gaddf7bc2cde2b99f5f00b09c8e39f9a73"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_IBI_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 7 - IBI. </p>

<p>Referenced by <a class="el" href="group___overview.html#gae0d7f9bd9e10d5de348154d823d7bea0">XI3c_IbiRecv()</a>, and <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga11f5367ba0a41f97993c47cff79ad7f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RD_FIFO_ALMOST_FULL_MASK&#160;&#160;&#160;0x00001000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 12 - Read Fifo almost Full. </p>

</div>
</div>
<a class="anchor" id="gafb3daf54b287d6bde50bd16b2ce6b28d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RD_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 15 - Read FIFO empty. </p>

</div>
</div>
<a class="anchor" id="gaa0b74281de2f580f72138e92fa448244"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RD_FULL_MASK&#160;&#160;&#160;0x00000040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 6 - Read Fifo Full. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, and <a class="el" href="group___overview.html#ga65bbec96638b9e2f5627452ac9a9ae48">XI3c_MasterRecv()</a>.</p>

</div>
</div>
<a class="anchor" id="ga4eca8a991fb3151108c6933bfeb51c5e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RE_OFFSET&#160;&#160;&#160;0x18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Status Event Enable(Rising Edge) Register. </p>

</div>
</div>
<a class="anchor" id="ga070c1bd5720ca64e0a76e8afa6d6b0a6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RESP_FULL_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 3 - Resp Fifo Full. </p>

</div>
</div>
<a class="anchor" id="gabdb31954696a689f6a99d67ec180e6e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RESP_NOT_EMPTY_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 4 - Resp Fifo not empty. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>, <a class="el" href="group___overview.html#gae0d7f9bd9e10d5de348154d823d7bea0">XI3c_IbiRecv()</a>, <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, <a class="el" href="group___overview.html#ga65bbec96638b9e2f5627452ac9a9ae48">XI3c_MasterRecv()</a>, <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>, and <a class="el" href="group___overview.html#ga64fba1f66dc69a20b21f414cccb90752">XI3c_SlaveInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga685b9e09fe59849441299b87aeaa1251"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_RETURN_ROLE_REQ_ACK_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 11 - Received ACK on controller role request back. </p>

</div>
</div>
<a class="anchor" id="ga8db15484dd9ba5bbfcd041249b63ef4c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_STATUS_OFFSET&#160;&#160;&#160;0x14</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Status Event Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, and <a class="el" href="group___overview.html#ga64fba1f66dc69a20b21f414cccb90752">XI3c_SlaveInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gacb00abdbc75747d0a18d1e8410d07a68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 5 - Write Fifo Full. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, and <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>.</p>

</div>
</div>
<a class="anchor" id="gacf48010016e4266ae11f968791685435"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_INTR_WR_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00004000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 14 - Write FIFO empty. </p>

</div>
</div>
<a class="anchor" id="ga6707c3c86ecbb35f037252f3db9b57aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_IsDyncAddrAssigned</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                         \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>)) &amp; <a class="code" href="group___overview.html#ga7e4d65a8da33e49fda2aeba47497ab6a">XI3C_SR_SLV_DYNC_ADDR_DONE_MASK</a>)</div>
<div class="ttc" id="group___overview_html_ga0a3b3b24854197b7342e82f6d472ad60"><div class="ttname"><a href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a></div><div class="ttdeci">#define XI3C_SR_OFFSET</div><div class="ttdoc">Status Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:61</div></div>
<div class="ttc" id="group___overview_html_ga7e4d65a8da33e49fda2aeba47497ab6a"><div class="ttname"><a href="group___overview.html#ga7e4d65a8da33e49fda2aeba47497ab6a">XI3C_SR_SLV_DYNC_ADDR_DONE_MASK</a></div><div class="ttdeci">#define XI3C_SR_SLV_DYNC_ADDR_DONE_MASK</div><div class="ttdoc">BIT 19 - Dynamic address assigned to slave. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:153</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Check the dynamic address assignment status of I3C in slave mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>1 if address assigned. 0 if address not assigned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga6707c3c86ecbb35f037252f3db9b57aa" title="Check the dynamic address assignment status of I3C in slave mode. ">XI3c_IsDyncAddrAssigned(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>, and <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="gad5e1fadfb7307f4993cc96f32efe43e4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_IsRespAvailable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                         \</div>
<div class="line">                       <a class="code" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>)) &amp; <a class="code" href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">XI3C_SR_RESP_NOT_EMPTY_MASK</a>)</div>
<div class="ttc" id="group___overview_html_ga0a3b3b24854197b7342e82f6d472ad60"><div class="ttname"><a href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a></div><div class="ttdeci">#define XI3C_SR_OFFSET</div><div class="ttdoc">Status Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:61</div></div>
<div class="ttc" id="group___overview_html_gac9b9816a95d893384063e7fe2ce892ac"><div class="ttname"><a href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">XI3C_SR_RESP_NOT_EMPTY_MASK</a></div><div class="ttdeci">#define XI3C_SR_RESP_NOT_EMPTY_MASK</div><div class="ttdoc">BIT 4 - Resp Fifo not empty. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:137</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Check the response status of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>1 if response available. 0 if response not available.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#gad5e1fadfb7307f4993cc96f32efe43e4" title="Check the response status of I3C. ">XI3c_IsRespAvailable(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga698dbf261cef62aea0e39e26e36444dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_MWL_MRL&#160;&#160;&#160;0x74</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Maximum Write and Max Read length. </p>

</div>
</div>
<a class="anchor" id="ga71c271412e577611810fe80fe0f51703"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_OD_SCL_HIGH_TIME_OFFSET&#160;&#160;&#160;0x54</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C OD SCL HIGH Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5455e0616c1f4d0728b493ea0fb92b6f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_OD_SCL_LOW_TIME_OFFSET&#160;&#160;&#160;0x58</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C OD SCL LOW Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_RD_FIFO_OFFSET&#160;&#160;&#160;0x28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C Read Data FIFO Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga0c07229c964da96edd30443b424def69"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_RD_FIFO_RESET_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 3 - Read fifo reset. </p>

</div>
</div>
<a class="anchor" id="gac7ca28d237412cebb19bb2d5bde6eae6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_RdFifoLevel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,             \</div>
<div class="line">                           <a class="code" href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a>) &amp;             \</div>
<div class="line">              XI3C_16BITS_MASK)</div>
<div class="ttc" id="group___overview_html_ga699026be01649fea70621f96ab6f8dec"><div class="ttname"><a href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a></div><div class="ttdeci">#define XI3C_FIFO_LVL_STATUS_1_OFFSET</div><div class="ttdoc">I3C RESP &amp;amp; RD FIFO LVL Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:70</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Read RD FIFO LEVEL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6" title="Read RD FIFO LEVEL. ">XI3c_RdFifoLevel(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>, <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, and <a class="el" href="group___overview.html#ga838caa68513d3391c4f3e85705671f46">XI3c_MasterRecvPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="gab12a89030f0016bebe64fac8878cc57f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XI3c_In32((BaseAddress) + (u32)(RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read an I3C register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>contains the offset from the 1st register of the device to select the specific register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value read from the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: u32 XI3c_ReadReg(u32 BaseAddress. int RegOffset) </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, <a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo()</a>, and <a class="el" href="group___overview.html#ga64fba1f66dc69a20b21f414cccb90752">XI3c_SlaveInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gaeeafc8dc6cd85b8ecc8af8d545efa2d6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_RESET_OFFSET&#160;&#160;&#160;0x04</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Soft Reset Register. </p>

</div>
</div>
<a class="anchor" id="gacadbf79a1e643cce18a063a2289a1105"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_RESP_FIFO_RESET_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 4 - Response fifo reset. </p>

</div>
</div>
<a class="anchor" id="ga2c063c7296db1c51db465c7e3609a8ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_RESP_STATUS_FIFO_OFFSET&#160;&#160;&#160;0x2C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C Response status FIFO Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf68a808c2f04670d1b37a874ab0368dd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_RespFifoLevel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)((<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,            \</div>
<div class="line">                            <a class="code" href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a>) &amp;            \</div>
<div class="line">                            XI3C_MSB_16BITS_MASK) &gt;&gt; XI3C_RESP_LVL_SHIFT)</div>
<div class="ttc" id="group___overview_html_ga699026be01649fea70621f96ab6f8dec"><div class="ttname"><a href="group___overview.html#ga699026be01649fea70621f96ab6f8dec">XI3C_FIFO_LVL_STATUS_1_OFFSET</a></div><div class="ttdeci">#define XI3C_FIFO_LVL_STATUS_1_OFFSET</div><div class="ttdoc">I3C RESP &amp;amp; RD FIFO LVL Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:70</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Read RESP FIFO LEVEL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u16 <a class="el" href="group___overview.html#gaf68a808c2f04670d1b37a874ab0368dd" title="Read RESP FIFO LEVEL. ">XI3c_RespFifoLevel(XI3c *InstancePtr)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga0836e481b2a27d2f3b7f2992d7c1be0f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_RespFifoNotEmpty</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u32)(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,             \</div>
<div class="line">                            <a class="code" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>) &amp;                           <a class="code" href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">\</a></div>
<div class="line"><a class="code" href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">                            XI3C_SR_RESP_NOT_EMPTY_MASK</a>)</div>
<div class="ttc" id="group___overview_html_ga0a3b3b24854197b7342e82f6d472ad60"><div class="ttname"><a href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a></div><div class="ttdeci">#define XI3C_SR_OFFSET</div><div class="ttdoc">Status Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:61</div></div>
<div class="ttc" id="group___overview_html_gac9b9816a95d893384063e7fe2ce892ac"><div class="ttname"><a href="group___overview.html#gac9b9816a95d893384063e7fe2ce892ac">XI3C_SR_RESP_NOT_EMPTY_MASK</a></div><div class="ttdeci">#define XI3C_SR_RESP_NOT_EMPTY_MASK</div><div class="ttdoc">BIT 4 - Resp Fifo not empty. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:137</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Check Response FIFO empty status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f" title="Check Response FIFO empty status. ">XI3c_RespFifoNotEmpty(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>, and <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga502dee04797d325155788141fa7db242"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_RxFifoNotEmpty</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u32)(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,             \</div>
<div class="line">                            <a class="code" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>) &amp;                           <a class="code" href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">\</a></div>
<div class="line"><a class="code" href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">                            XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</a>)</div>
<div class="ttc" id="group___overview_html_ga0a3b3b24854197b7342e82f6d472ad60"><div class="ttname"><a href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a></div><div class="ttdeci">#define XI3C_SR_OFFSET</div><div class="ttdoc">Status Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:61</div></div>
<div class="ttc" id="group___overview_html_ga921e87b7a626211a1983b98dc3b22977"><div class="ttname"><a href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</a></div><div class="ttdeci">#define XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</div><div class="ttdoc">BIT 15 - Read FIFO empty. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:152</div></div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Check Read FIFO empty status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group___overview.html#ga502dee04797d325155788141fa7db242" title="Check Read FIFO empty status. ">XI3c_RxFifoNotEmpty(XI3c *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>, and <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga19907a1f8fccab4045cec4f33a0a019b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SCL_HIGH_TIME_OFFSET&#160;&#160;&#160;0x38</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C SCL HIGH Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gacac5bc3663c87ed53678bbb88c58a737"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SCL_LOW_TIME_OFFSET&#160;&#160;&#160;0x3C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C SCL LOW Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gac98f0b52e9c9c40ccf5b41cd8fce94d6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SDA_HOLD_TIME_OFFSET&#160;&#160;&#160;0x40</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C SDA HOLD Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8879a5913307a7fef1085a98a985306b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetBusIdleTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>, <a class="code" href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a>,\</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga5eceedf78b84fdf70668668722c671af"><div class="ttname"><a href="group___overview.html#ga5eceedf78b84fdf70668668722c671af">XI3C_BUS_IDLE_OFFSET</a></div><div class="ttdeci">#define XI3C_BUS_IDLE_OFFSET</div><div class="ttdoc">I3C CONTROLLER BUS IDLE Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:74</div></div>
</div><!-- fragment -->
<p>Sets bus idle time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is bus idle time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga8879a5913307a7fef1085a98a985306b" title="Sets bus idle time of I3C. ">XI3c_SetBusIdleTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga71646fcfb10ac4f32b64f559fc5bc355"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetCapsFormat1</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap1, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap2, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap3, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap4&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#gadeb959adfc801c98b78b2efa8fc09f8b">XI3C_GETCAPS_REG0</a>,                                \</div>
<div class="line">                      (((Caps4 &amp; XI3C_8BITS_MASK) &lt;&lt; XI3C_CAPS4_SHIFT) |\</div>
<div class="line">                      ((Caps3 &amp; XI3C_8BITS_MASK) &lt;&lt; XI3C_CAPS3_SHIFT) | \</div>
<div class="line">                      ((Caps2 &amp; XI3C_8BITS_MASK) &lt;&lt; XI3C_CAPS2_SHIFT) | \</div>
<div class="line">                       (Caps1 &amp; XI3C_8BITS_MASK)))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gadeb959adfc801c98b78b2efa8fc09f8b"><div class="ttname"><a href="group___overview.html#gadeb959adfc801c98b78b2efa8fc09f8b">XI3C_GETCAPS_REG0</a></div><div class="ttdeci">#define XI3C_GETCAPS_REG0</div><div class="ttdoc">Target Device Format 1 Capabilities. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:85</div></div>
</div><!-- fragment -->
<p>Sets device capabilities format1. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Caps1</td><td>of target device. </td></tr>
    <tr><td class="paramname">Caps2</td><td>of target device. </td></tr>
    <tr><td class="paramname">Caps3</td><td>of target device. </td></tr>
    <tr><td class="paramname">Caps4</td><td>of target device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XI3c_SetCapsFormat1(<a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> *InstancePtr, u8 Cap1, u8 Cap2, u8 Cap3, u8 Cap4) </dd></dl>

</div>
</div>
<a class="anchor" id="ga0dbc4d41771a2b6ca9da3c230b172562"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetCapsFormat2</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap1, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Cap2&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">XI3C_GETCAPS_REG1</a>,                                \</div>
<div class="line">                      (((Caps2 &amp; XI3C_8BITS_MASK) &lt;&lt; XI3C_CAPS2_SHIFT) |\</div>
<div class="line">                       (Caps1 &amp; XI3C_8BITS_MASK)))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="group___overview_html_ga3a5ef5be5a8d1b70ce3fb3da4620c04f"><div class="ttname"><a href="group___overview.html#ga3a5ef5be5a8d1b70ce3fb3da4620c04f">XI3C_GETCAPS_REG1</a></div><div class="ttdeci">#define XI3C_GETCAPS_REG1</div><div class="ttdoc">Target Device Format 2 Capabilities. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:86</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets device capabilities format2. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Caps1</td><td>of target device. </td></tr>
    <tr><td class="paramname">Caps2</td><td>of target device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group___overview.html#ga0dbc4d41771a2b6ca9da3c230b172562" title="Sets device capabilities format2. ">XI3c_SetCapsFormat2(XI3c *InstancePtr, u8 Cap1, u8 Cap2)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gad62fd667f9befb43452d4d8627501520"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetDeviceStatus</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Format1, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Format2&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga6da19b220a65d5ada6af1c9962d27184">XI3C_GETSTATUS</a>,                                   \</div>
<div class="line">                      ((Format1 &amp; XI3C_16BITS_MASK) |                   \</div>
<div class="line">                        ((Format2 &amp; XI3C_16BITS_MASK) &lt;&lt;                \</div>
<div class="line">                         XI3C_GETSTATUS_FORMAT2_SHIFT)))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga6da19b220a65d5ada6af1c9962d27184"><div class="ttname"><a href="group___overview.html#ga6da19b220a65d5ada6af1c9962d27184">XI3C_GETSTATUS</a></div><div class="ttdeci">#define XI3C_GETSTATUS</div><div class="ttdoc">Target Device current Status. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:84</div></div>
</div><!-- fragment -->
<p>Sets device status of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Format1</td><td>value of Device status. </td></tr>
    <tr><td class="paramname">Format2</td><td>value of Device status.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XI3c_SetDeviceStatus(<a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> *InstancePtr, u16 Format1, u16 Format2) </dd></dl>

</div>
</div>
<a class="anchor" id="ga6ea989327a7525174a52188888e4434f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetMaxDataSpeed</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Format1, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Format3&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#gab6f648bc7840eb8d61cb3c5d06d3f613">XI3C_GETMXDS</a>,                                     \</div>
<div class="line">                      ((Format1 &amp; XI3C_16BITS_MASK) |                   \</div>
<div class="line">                        ((Format3 &amp; XI3C_8BITS_MASK) &lt;&lt;                 \</div>
<div class="line">                         XI3C_GETMXDS_FORMAT3_DATA_SHIFT)))</div>
<div class="ttc" id="group___overview_html_gab6f648bc7840eb8d61cb3c5d06d3f613"><div class="ttname"><a href="group___overview.html#gab6f648bc7840eb8d61cb3c5d06d3f613">XI3C_GETMXDS</a></div><div class="ttdeci">#define XI3C_GETMXDS</div><div class="ttdoc">Target Device Max Data Speed. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:83</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets device Max data speed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Format1</td><td>value of Device status. </td></tr>
    <tr><td class="paramname">Format3</td><td>value of Device status.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XI3c_SetMaxDataSpeed(<a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> *InstancePtr, u16 Format1, u8 Format3) </dd></dl>

</div>
</div>
<a class="anchor" id="ga7efd0f29eba1bd3d20f9ecdf62f14c0b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetSclHighTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a>,                        \</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga19907a1f8fccab4045cec4f33a0a019b"><div class="ttname"><a href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SCL_HIGH_TIME_OFFSET</div><div class="ttdoc">I3C SCL HIGH Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:71</div></div>
</div><!-- fragment -->
<p>Sets scl high time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is scl high time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga7efd0f29eba1bd3d20f9ecdf62f14c0b" title="Sets scl high time of I3C. ">XI3c_SetSclHighTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga96598e0e4ac5fc98159cbbe34f266976"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetSclLowTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a>,                         \</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gacac5bc3663c87ed53678bbb88c58a737"><div class="ttname"><a href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SCL_LOW_TIME_OFFSET</div><div class="ttdoc">I3C SCL LOW Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:72</div></div>
</div><!-- fragment -->
<p>Sets scl low time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is scl low time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga96598e0e4ac5fc98159cbbe34f266976" title="Sets scl low time of I3C. ">XI3c_SetSclLowTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga1d1aac5f2db8f3623f1897f92ad8425c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetSclOdHighTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a>,                     \</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="group___overview_html_ga71c271412e577611810fe80fe0f51703"><div class="ttname"><a href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_OD_SCL_HIGH_TIME_OFFSET</div><div class="ttdoc">I3C OD SCL HIGH Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:78</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets Scl open drain high time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is Scl open drain high time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga1d1aac5f2db8f3623f1897f92ad8425c" title="Sets Scl open drain high time of I3C. ">XI3c_SetSclOdHighTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gad6571c88c0dfe0e735a30264e041c809"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetSclOdLowTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a>,                      \</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="group___overview_html_ga5455e0616c1f4d0728b493ea0fb92b6f"><div class="ttname"><a href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_OD_SCL_LOW_TIME_OFFSET</div><div class="ttdoc">I3C OD SCL LOW Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:79</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets Scl open drain low time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is Scl open drain low time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#gad6571c88c0dfe0e735a30264e041c809" title="Sets Scl open drain low time of I3C. ">XI3c_SetSclOdLowTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga3ca247fdf2e014bc7974c8789f5cb1fa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetSdaHoldTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,                  \</div>
<div class="line">                      <a class="code" href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a>,                        \</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gac98f0b52e9c9c40ccf5b41cd8fce94d6"><div class="ttname"><a href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a></div><div class="ttdeci">#define XI3C_SDA_HOLD_TIME_OFFSET</div><div class="ttdoc">I3C SDA HOLD Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:73</div></div>
</div><!-- fragment -->
<p>Sets sda hold time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is sda hold time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga3ca247fdf2e014bc7974c8789f5cb1fa" title="Sets sda hold time of I3C. ">XI3c_SetSdaHoldTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gad40e322019eadf7b34ba6ff527097295"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetThdStartTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>, <a class="code" href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a>,\</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga7b6019d7d90a6ffe16d5031c677da546"><div class="ttname"><a href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a></div><div class="ttdeci">#define XI3C_THD_START_OFFSET</div><div class="ttdoc">I3C START HOLD Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:76</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets Thd Start time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is Thd Start time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#gad40e322019eadf7b34ba6ff527097295" title="Sets Thd Start time of I3C. ">XI3c_SetThdStartTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga4f4c510d9d1c0d109cff9051c15423fc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetTsuStartTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>, <a class="code" href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a>,\</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_gaad8bc7285bee2d4b07caf0be75751909"><div class="ttname"><a href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a></div><div class="ttdeci">#define XI3C_TSU_START_OFFSET</div><div class="ttdoc">I3C START SETUP Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:75</div></div>
</div><!-- fragment -->
<p>Sets Tsu Start time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is Tsu Start time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#ga4f4c510d9d1c0d109cff9051c15423fc" title="Sets Tsu Start time of I3C. ">XI3c_SetTsuStartTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="gafd55de5f0c3287b23bdc9ee3b1981fd4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_SetTsuStopTime</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Val&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>, <a class="code" href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a>,\</div>
<div class="line">                      (Val &amp; XI3C_18BITS_MASK))</div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="group___overview_html_gaf9c766c72c30099de526c5d78a99ba5c"><div class="ttname"><a href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a></div><div class="ttdeci">#define XI3C_TSU_STOP_OFFSET</div><div class="ttdoc">I3C STOP Setup Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:77</div></div>
<div class="ttc" id="group___overview_html_ga6d1adc84977bc35bde5d82bb4a874d6b"><div class="ttname"><a href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a></div><div class="ttdeci">#define XI3c_WriteReg(BaseAddress, RegOffset, RegisterValue)</div><div class="ttdoc">Write an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:292</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
</div><!-- fragment -->
<p>Sets Tsu Stop time of I3C. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Val</td><td>is Tsu Stop time value to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to update other timing parameters if required. C-style signature: void <a class="el" href="group___overview.html#gafd55de5f0c3287b23bdc9ee3b1981fd4" title="Sets Tsu Stop time of I3C. ">XI3c_SetTsuStopTime(XI3c *InstancePtr, u32 Val)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ga1da2b90b0f8ce89043634891a7e9ba49"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SOFT_RESET_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 0 - Reset. </p>

</div>
</div>
<a class="anchor" id="ga07f073cf0ff84797b4d805541b4fbec7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_BUS_BUSY_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 0 - Bus Busy. </p>

</div>
</div>
<a class="anchor" id="ga757f54fcb43fbdfe0ade99df244a68a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_BUS_BUSY_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 0 - Bus Busy. </p>

</div>
</div>
<a class="anchor" id="ga59481855d3ba5232e103325915b8c9c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CLK_STALL_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 - Clock Stall. </p>

</div>
</div>
<a class="anchor" id="ga6c649b5952826e117e67f92d4aee240a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CLK_STALL_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 1 - Clock Stall. </p>

</div>
</div>
<a class="anchor" id="ga081fe15e4db5cd138cb5a79161530726"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CMD_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00002000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 13 - CMD FIFO empty. </p>

</div>
</div>
<a class="anchor" id="ga734f3b7a052444daaed24d346b67cd43"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CMD_FULL_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 2 - Cmd Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga1869fb29215628f67e0a0414eee54d0e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CMD_FULL_SHIFT&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 2 - Cmd Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga28fcad7bbd4d188d5f7115fc9a6c124a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_CTRL_ROLE_REQUEST_MASK&#160;&#160;&#160;0x00000200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 9 - Received control role request. </p>

</div>
</div>
<a class="anchor" id="ga72bccabb2e243917849140d2fa491bd7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_ERROR_TYPE_CE3_MASK&#160;&#160;&#160;0x00000400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 10 - This field will be set if there is no START coming from the new Controller that has took over the Role. </p>

</div>
</div>
<a class="anchor" id="gab6c4dfdb3896048df2fe69d50d72f081"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_HJ_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 8 - Hot join. </p>

</div>
</div>
<a class="anchor" id="ga036ea1c62d3f28a118f5dcd137c128e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_IBI_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 7 - IBI. </p>

</div>
</div>
<a class="anchor" id="ga0a3b3b24854197b7342e82f6d472ad60"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_OFFSET&#160;&#160;&#160;0x10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Status Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="gae32d0edcf3609f4aa31a8385861d6f00"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RD_FIFO_ALMOST_FULL_MASK&#160;&#160;&#160;0x00001000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 12 - Read Fifo almost Full. </p>

</div>
</div>
<a class="anchor" id="ga921e87b7a626211a1983b98dc3b22977"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RD_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 15 - Read FIFO empty. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="gabb62f870d6eaf9a0e84455a3b8f95802"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RD_FULL_MASK&#160;&#160;&#160;0x00000040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 6 - Read Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga5ab43aee70ecb74f43a04a2b4288c5ef"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RD_FULL_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 6 - Read Fifo Full. </p>

</div>
</div>
<a class="anchor" id="gab3374e03a2587e874036d2f516a7de67"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RESP_FULL_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 3 - Resp Fifo Full. </p>

</div>
</div>
<a class="anchor" id="gafdbb91c4f4f0bad0b9a1c43ff32d9d34"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RESP_FULL_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 3 - Resp Fifo Full. </p>

</div>
</div>
<a class="anchor" id="gac9b9816a95d893384063e7fe2ce892ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RESP_NOT_EMPTY_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 4 - Resp Fifo not empty. </p>

</div>
</div>
<a class="anchor" id="ga77ec3c78d800fc0a33781122c40fb8b8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RESP_NOT_EMPTY_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 4 - Resp Fifo not empty. </p>

</div>
</div>
<a class="anchor" id="ga79bae274f84eac816db1b3abc42aae5c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_RETURN_ROLE_REQ_ACK_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 11 - Received ACK on controller role request back. </p>

</div>
</div>
<a class="anchor" id="ga7e4d65a8da33e49fda2aeba47497ab6a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_SLV_DYNC_ADDR_DONE_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 19 - Dynamic address assigned to slave. </p>

</div>
</div>
<a class="anchor" id="ga505303ab58a602428e0f9f4236c48b3b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_SLV_DYNC_ADDR_DONE_SHIFT&#160;&#160;&#160;19</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 19 - Dynamic address assigned to slave. </p>

</div>
</div>
<a class="anchor" id="gaddc84e40ea7fbdede29fc1d687d31c82"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_WR_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00004000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 14 - Write FIFO empty. </p>

</div>
</div>
<a class="anchor" id="gab8e7f9751ccb9a2bc60cbf3ef63ec5fe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_WR_FULL_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 5 - Write Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga9453d2e836832225cdb9166fbf2a509b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_SR_WR_FULL_SHIFT&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 5 - Write Fifo Full. </p>

</div>
</div>
<a class="anchor" id="ga4c64e1b8520dbdc358d94d36c3927256"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_TARGET_ADDR_BCR&#160;&#160;&#160;0x60</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C Target dynamic Address and BCR Register. </p>

</div>
</div>
<a class="anchor" id="ga7b6019d7d90a6ffe16d5031c677da546"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_THD_START_OFFSET&#160;&#160;&#160;0x4C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C START HOLD Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gaad8bc7285bee2d4b07caf0be75751909"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_TSU_START_OFFSET&#160;&#160;&#160;0x48</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C START SETUP Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf9c766c72c30099de526c5d78a99ba5c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_TSU_STOP_OFFSET&#160;&#160;&#160;0x50</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C STOP Setup Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>.</p>

</div>
</div>
<a class="anchor" id="gaa938ff976973faa16dd719be03700422"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_VERSION_OFFSET&#160;&#160;&#160;0x00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register offsets for the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> device. </p>
<p>Version Register </p>

</div>
</div>
<a class="anchor" id="ga38756ab021295465c1b621deb8d80ec2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_WR_FIFO_OFFSET&#160;&#160;&#160;0x24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>I3C Write Data FIFO Register. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8813d9d73c5f1c95bc5867d60b829d6d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3C_WR_FIFO_RESET_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>BIT 2 - Write fifo reset. </p>

</div>
</div>
<a class="anchor" id="ga0a979344e276171bf0bf87eb27c7ffd7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_WrFifoLevel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(u16)(<a class="code" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>(InstancePtr-&gt;<a class="code" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">Config</a>.<a class="code" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">BaseAddress</a>,               \</div>
<div class="line">                           <a class="code" href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a>) &amp; XI3C_16BITS_MASK)</div>
<div class="ttc" id="group___overview_html_gab12a89030f0016bebe64fac8878cc57f"><div class="ttname"><a href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a></div><div class="ttdeci">#define XI3c_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">Read an I3C register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:274</div></div>
<div class="ttc" id="struct_x_i3c___config_html_a5022354efb94520441dca651cb9643bc"><div class="ttname"><a href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a></div><div class="ttdeci">UINTPTR BaseAddress</div><div class="ttdoc">Base address of the device. </div><div class="ttdef"><b>Definition:</b> xi3c.h:735</div></div>
<div class="ttc" id="struct_x_i3c_html_a8a4d3a8c73221b302c6eedbdb4496b71"><div class="ttname"><a href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a></div><div class="ttdeci">XI3c_Config Config</div><div class="ttdoc">Configuration structure. </div><div class="ttdef"><b>Definition:</b> xi3c.h:778</div></div>
<div class="ttc" id="group___overview_html_ga2d2708084fb73a3e790473dcd71a8b46"><div class="ttname"><a href="group___overview.html#ga2d2708084fb73a3e790473dcd71a8b46">XI3C_FIFO_LVL_STATUS_OFFSET</a></div><div class="ttdeci">#define XI3C_FIFO_LVL_STATUS_OFFSET</div><div class="ttdoc">I3C CMD &amp;amp; WR FIFO LVL Register. </div><div class="ttdef"><b>Definition:</b> xi3c_hw.h:69</div></div>
</div><!-- fragment -->
<p>Read WR FIFO LEVEL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the instance of I3C</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7" title="Read WR FIFO LEVEL. ">XI3c_WrFifoLevel(XI3cPsx *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>, <a class="el" href="group___overview.html#ga268011500642adc668ce75abbe555a6a">XI3c_MasterSendPolled()</a>, <a class="el" href="group___overview.html#ga28021172cfe5d1d3dfb20e8f3f58c94f">XI3c_SlaveSend()</a>, and <a class="el" href="group___overview.html#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">XI3c_SlaveSendPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="ga6d1adc84977bc35bde5d82bb4a874d6b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XI3c_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegisterValue&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XI3c_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write an I3C register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>contains the offset from the 1st register of the device to select the specific register. </td></tr>
    <tr><td class="paramname">RegisterValue</td><td>is the value to be written to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-Style signature: void <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b" title="Write an I3C register. ">XI3c_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)</a> </dd></dl>

<p>Referenced by <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, <a class="el" href="group___overview.html#ga8bdcc22a96e0b2be5e806b29761cc83a">XI3c_SetSClk()</a>, <a class="el" href="group___overview.html#ga64fba1f66dc69a20b21f414cccb90752">XI3c_SlaveInterruptHandler()</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

</div>
</div>
<h2 class="groupheader">Typedef Documentation</h2>
<a class="anchor" id="ga7a0b155b789c03dd574c94bbf0d195db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">typedef void(* XI3c_IntrHandler)(u32 StatusEvent)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The handler data type allows the user to define a callback function to respond to interrupt events in the system. </p>
<p>This function is executed in interrupt context, so amount of processing should be minimized.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallBackRef</td><td>is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer. </td></tr>
    <tr><td class="paramname">StatusEvent</td><td>indicates one or more status events that occurred. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gaa01a28908016aac835dd4493a0c6413e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3C_BusInit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Initializes the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> slaves devices by disable/enable events and reset dynamic addresses. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; SDR mode</p>
<p>&lt; SDR mode</p>
<p>&lt; SDR mode </p>

<p>References <a class="el" href="group___overview.html#ga822775f0526bd47739bdf842954d874f">XI3c_SendTransferCmd()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>, <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>, and <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga3a6f3237b5eecb5d9144c3254dbab088"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a> *&#160;</td>
          <td class="paramname"><em>ConfigPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Initializes a specific <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance such that the driver is ready to use. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">ConfigPtr</td><td>is a reference to a structure containing information about a specific I3C device. This function initializes an InstancePtr object for a specific device specified by the contents of Config. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr-&gt;BaseAddress for this parameter, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The return value is XST_SUCCESS if successful.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Master mode</p>
<p>&lt; Slave mode </p>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a5fa885b8dd7a51cbbfb76d040982e083">XI3c::CurDeviceCount</a>, <a class="el" href="struct_x_i3c___config.html#a07fad66cc76f37f2f5a2f50ed583efe9">XI3c_Config::DeviceCount</a>, <a class="el" href="struct_x_i3c___config.html#a8f3877da5e1a217b50c83f33f7f4b6cf">XI3c_Config::DeviceId</a>, <a class="el" href="struct_x_i3c___config.html#a4bb1a9c36ac58f572e9246a2d33a6fdc">XI3c_Config::DeviceRole</a>, <a class="el" href="struct_x_i3c___config.html#a327ead358c68ebdffab43d79bec1aa33">XI3c_Config::HjCapable</a>, <a class="el" href="struct_x_i3c___config.html#a6b77e6c8d08a475b719cafeb7f39ffed">XI3c_Config::IbiCapable</a>, <a class="el" href="struct_x_i3c___config.html#afcc9598c42b89940e46ed396994f62cb">XI3c_Config::InputClockHz</a>, <a class="el" href="struct_x_i3c.html#a50fcb290a96dc55a925ae6609ac639f5">XI3c::IsReady</a>, <a class="el" href="struct_x_i3c___config.html#a1ccd35fbd357de82147eed63989ede57">XI3c_Config::RwFifoDepth</a>, <a class="el" href="struct_x_i3c___config.html#ac06902bd1139701f9309539b84ca9acf">XI3c_Config::WrThreshold</a>, <a class="el" href="group___overview.html#gaa01a28908016aac835dd4493a0c6413e">XI3C_BusInit()</a>, <a class="el" href="group___overview.html#ga52d0b05e4f81129c7a75cefdf0ef5621">XI3c_ConfigIbi()</a>, <a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign()</a>, <a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>, <a class="el" href="group___overview.html#ga0cc6f9c3c763acf9b012c571851dcf3a">XI3C_INTR_HJ_MASK</a>, and <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>, <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>, <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>, and <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga52d0b05e4f81129c7a75cefdf0ef5621"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_ConfigIbi </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DevCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This configure target address and BCR register values of available devices to the controller RAM. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">DevCount</td><td>is the number of slave devices present.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c.html#a50fcb290a96dc55a925ae6609ac639f5">XI3c::IsReady</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ga87d285dd413cf579d43a6eda306619ce"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_DynaAddrAssign </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DynaAddr</em>[], </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DevCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function sends dynamic Address Assignment for available devices. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">DynaAddr</td><td>is an array of dynamic addresses. </td></tr>
    <tr><td class="paramname">DevCount</td><td>is the number of slave devices present.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_FAILURE if any error.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Enable repeated start</p>
<p>&lt; Broadcast address</p>
<p>&lt; BCR - RecvBuffer[6]</p>
<p>&lt; DCR - RecvBuffer[7]</p>
<p>&lt; Dynamic address </p>

<p>References <a class="el" href="struct_x_i3c___slave_info.html#a77ddc55dd4734e372a1926b5de098a1b">XI3c_SlaveInfo::Bcr</a>, <a class="el" href="struct_x_i3c.html#a5fa885b8dd7a51cbbfb76d040982e083">XI3c::CurDeviceCount</a>, <a class="el" href="struct_x_i3c___slave_info.html#af7262efd435d0749c002fedd6008d9ec">XI3c_SlaveInfo::Dcr</a>, <a class="el" href="struct_x_i3c___slave_info.html#a66a7ea44945d908fb3a1e4a1fad04256">XI3c_SlaveInfo::DynaAddr</a>, <a class="el" href="struct_x_i3c___slave_info.html#a51a5fff2dd7aea2bd28bc3e1cdbaade2">XI3c_SlaveInfo::Id</a>, <a class="el" href="struct_x_i3c.html#a50fcb290a96dc55a925ae6609ac639f5">XI3c::IsReady</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#ga838caa68513d3391c4f3e85705671f46">XI3c_MasterRecvPolled()</a>, <a class="el" href="group___overview.html#ga822775f0526bd47739bdf842954d874f">XI3c_SendTransferCmd()</a>, <a class="el" href="struct_x_i3c.html#a3eee7c94363964228184c09bfa073b22">XI3c::XI3c_SlaveInfoTable</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="group___overview.html#ga3a6f3237b5eecb5d9144c3254dbab088">XI3c_CfgInitialize()</a>, and <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gafb601913b993b4c23cb89306aa630be5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_FillCmdFifo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fill I3C Command fifo. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">TransferCmd</td><td>is a pointer to the XI3c_Cmd instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Command Type: 0 to 3 bits</p>
<p>&lt; Repeated start or Termination on Completion: 4th bit</p>
<p>&lt; Parity Error Check: 5th bit</p>
<p>&lt; RW: 8th bit + Device address: 9 to 15 bits</p>
<p>&lt; No.of bytes R/W to/from R/W FIFOs</p>
<p>&lt; Transaction ID </p>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="group___overview.html#ga310ed8a56b21fca347c2cc0b3aa7f2f9">XI3C_CMD_FIFO_OFFSET</a>, and <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga65bbec96638b9e2f5627452ac9a9ae48">XI3c_MasterRecv()</a>, <a class="el" href="group___overview.html#ga838caa68513d3391c4f3e85705671f46">XI3c_MasterRecvPolled()</a>, <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>, <a class="el" href="group___overview.html#ga268011500642adc668ce75abbe555a6a">XI3c_MasterSendPolled()</a>, and <a class="el" href="group___overview.html#ga822775f0526bd47739bdf842954d874f">XI3c_SendTransferCmd()</a>.</p>

</div>
</div>
<a class="anchor" id="gae0d7f9bd9e10d5de348154d823d7bea0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_IbiRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function setup for receive during IBI in interrupt mode. </p>
<p>It enables the required interrupts for performing read operation during IBI.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the recv buffer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_NO_DATA if message buffer is NULL.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>, <a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>, <a class="el" href="group___overview.html#gaddf7bc2cde2b99f5f00b09c8e39f9a73">XI3C_INTR_IBI_MASK</a>, and <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>.</p>

</div>
</div>
<a class="anchor" id="ga09a7b530e37d1df22d1373966e826cf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_IbiRecvPolled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function receives data during IBI in polled mode. </p>
<p>It polls the data register for data to come in during IBI. If master fails to read data due to any error, it will return with status.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the recv buffer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_RECV_ERROR if any error.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a745614fa4b0314ca47aa31fd89ab49b7">XI3c::RecvByteCount</a>, <a class="el" href="group___overview.html#ga199da98d8ddcd495482b436d294ec75d">TIMEOUT_COUNTER</a>, <a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">XI3c_RdFifoLevel</a>, <a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo()</a>, <a class="el" href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f">XI3c_RespFifoNotEmpty</a>, <a class="el" href="group___overview.html#ga502dee04797d325155788141fa7db242">XI3c_RxFifoNotEmpty</a>, <a class="el" href="group___overview.html#ga0a3b3b24854197b7342e82f6d472ad60">XI3C_SR_OFFSET</a>, and <a class="el" href="group___overview.html#ga921e87b7a626211a1983b98dc3b22977">XI3C_SR_RD_FIFO_NOT_EMPTY_MASK</a>.</p>

</div>
</div>
<a class="anchor" id="ga8212bca3426c2ca6a284e5de2a5a9180"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a>* XI3c_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Looks up the device configuration based on the unique device ID. </p>
<p>A table contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>contains the ID of the device to look up the configuration for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the configuration found or NULL if the specified device ID was not found. See xi3c.h for the definition of <a class="el" href="struct_x_i3c___config.html" title="This typedef contains configuration information for the device. ">XI3c_Config</a>.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group___overview.html#ga71e0cc721aa929d7f8e04206061d97c9">XI3c_ConfigTable</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>, <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>, <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>, and <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8c4e3e321553508d75097bebe04d0cf5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_MasterInterruptHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The interrupt handler for the master mode. </p>
<p>It does the protocol handling for the interrupt-driven transfers.</p>
<p>If the Master is receiving data then the data is read from the FIFO and the Master has to request for more data (if there is more data to receive). If all the data has been received then a completion event is signalled to the upper layer by calling the callback handler. It is an error if the amount of received data is more than expected.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a5fa885b8dd7a51cbbfb76d040982e083">XI3c::CurDeviceCount</a>, <a class="el" href="struct_x_i3c.html#a0c086a67f034487baa4ea845f7a35a13">XI3c::Error</a>, <a class="el" href="struct_x_i3c___config.html#a6b77e6c8d08a475b719cafeb7f39ffed">XI3c_Config::IbiCapable</a>, <a class="el" href="struct_x_i3c.html#a745614fa4b0314ca47aa31fd89ab49b7">XI3c::RecvByteCount</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="struct_x_i3c.html#a42264face85bd7505cf2eef5b1d173c8">XI3c::StatusHandler</a>, <a class="el" href="group___overview.html#ga6e84fcb954a3294f93ef7c65d74c22d8">XI3c_DisableFEInterrupts</a>, <a class="el" href="group___overview.html#gaa44c7fcb3f5568047c20e274f1e0de37">XI3c_DisableREInterrupts</a>, <a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign()</a>, <a class="el" href="group___overview.html#ga0cc6f9c3c763acf9b012c571851dcf3a">XI3C_INTR_HJ_MASK</a>, <a class="el" href="group___overview.html#gaddf7bc2cde2b99f5f00b09c8e39f9a73">XI3C_INTR_IBI_MASK</a>, <a class="el" href="group___overview.html#gaa0b74281de2f580f72138e92fa448244">XI3C_INTR_RD_FULL_MASK</a>, <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>, <a class="el" href="group___overview.html#ga8db15484dd9ba5bbfcd041249b63ef4c">XI3C_INTR_STATUS_OFFSET</a>, <a class="el" href="group___overview.html#gacb00abdbc75747d0a18d1e8410d07a68">XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK</a>, <a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">XI3c_RdFifoLevel</a>, <a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>, <a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo()</a>, <a class="el" href="group___overview.html#ga2c063c7296db1c51db465c7e3609a8ac">XI3C_RESP_STATUS_FIFO_OFFSET</a>, <a class="el" href="group___overview.html#ga0836e481b2a27d2f3b7f2992d7c1be0f">XI3c_RespFifoNotEmpty</a>, <a class="el" href="group___overview.html#ga502dee04797d325155788141fa7db242">XI3c_RxFifoNotEmpty</a>, <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>, <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga65bbec96638b9e2f5627452ac9a9ae48"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_MasterRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a interrupt mode receive in master mode. </p>
<p>It sets the transfer size register so the slave can send data to us. The rest of the work is managed by interrupt handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Cmd</td><td>is a pointer to the XI3c_Cmd instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the recv buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be recv.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Controller uses byte count during bus transaction</p>
<p>&lt; Read operation </p>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a745614fa4b0314ca47aa31fd89ab49b7">XI3c::RecvByteCount</a>, <a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>, <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, <a class="el" href="group___overview.html#gaa0b74281de2f580f72138e92fa448244">XI3C_INTR_RD_FULL_MASK</a>, and <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>.</p>

<p>Referenced by <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga838caa68513d3391c4f3e85705671f46"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_MasterRecvPolled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a polled mode receive in master mode. </p>
<p>It repeatedly sets the transfer size register so the slave can send data to us. It polls the data register for data to come in. If master fails to read data due arbitration lost or any other error, will return with status.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Cmd</td><td>is a pointer to the XI3c_Cmd instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_RECV_ERROR if any error.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; DAA case</p>
<p>&lt; Controller uses byte count during bus transaction</p>
<p>&lt; Read operation </p>

<p>References <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a745614fa4b0314ca47aa31fd89ab49b7">XI3c::RecvByteCount</a>, <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, <a class="el" href="group___overview.html#gac7ca28d237412cebb19bb2d5bde6eae6">XI3c_RdFifoLevel</a>, and <a class="el" href="group___overview.html#gad2aab26f4e34599f22921e263af12e0d">XI3c_ReadRxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>, and <a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign()</a>.</p>

</div>
</div>
<a class="anchor" id="gab0d816198d0abc6dabb332390fbe5c79"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_MasterSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a interrupt mode send in master mode. </p>
<p>It sends data to the FIFO and waits for the slave to pick them up. If master fails to send data due arbitration lost or any other, will stop transfer with status.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Cmd</td><td>is a pointer to the XI3c_Cmd instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Controller uses byte count during bus transaction</p>
<p>&lt; Write operation </p>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="struct_x_i3c___config.html#ac06902bd1139701f9309539b84ca9acf">XI3c_Config::WrThreshold</a>, <a class="el" href="group___overview.html#ga03622c20170a3203409c18ac0efcd1e7">XI3c_EnableFEInterrupts</a>, <a class="el" href="group___overview.html#ga4f2003a310655cbf699490aca1b1b460">XI3c_EnableREInterrupts</a>, <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>, <a class="el" href="group___overview.html#gacb00abdbc75747d0a18d1e8410d07a68">XI3C_INTR_WR_FIFO_ALMOST_FULL_MASK</a>, <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga268011500642adc668ce75abbe555a6a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_MasterSendPolled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a polled mode send in master mode. </p>
<p>It sends data to the FIFO and waits for the slave to pick them up. If master fails to send data due arbitration lost or any other error, will stop transfer status.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Cmd</td><td>is a pointer to the XI3c_Cmd instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_SEND_ERROR if any error.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Controller uses byte count during bus transaction</p>
<p>&lt; Write operation </p>

<p>References <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, and <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="gad2aab26f4e34599f22921e263af12e0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_ReadRxFifo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read RX I3C FIFO. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a745614fa4b0314ca47aa31fd89ab49b7">XI3c::RecvByteCount</a>, <a class="el" href="group___overview.html#gaf877cfb0a2ceb2f0e73ca67ebc9c1e1c">XI3C_RD_FIFO_OFFSET</a>, and <a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga09a7b530e37d1df22d1373966e826cf2">XI3c_IbiRecvPolled()</a>, <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, and <a class="el" href="group___overview.html#ga838caa68513d3391c4f3e85705671f46">XI3c_MasterRecvPolled()</a>.</p>

</div>
</div>
<a class="anchor" id="ga822775f0526bd47739bdf842954d874f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SendTransferCmd </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XI3c_Cmd *&#160;</td>
          <td class="paramname"><em>Cmd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function sends the command. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">Cmd</td><td>is a pointer to the XI3c_Cmd. </td></tr>
    <tr><td class="paramname">Data</td><td>is the command value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_FAILURE if any error.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>&lt; Broadcast address</p>
<p>&lt; Write operation</p>
<p>&lt; SIze of the command is 8 bits </p>

<p>References <a class="el" href="struct_x_i3c.html#a50fcb290a96dc55a925ae6609ac639f5">XI3c::IsReady</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#gafb601913b993b4c23cb89306aa630be5">XI3c_FillCmdFifo()</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__daa__example_8c.html#a4e510a3047c3be2157e59ae100a26f97">I3cMasterDaaExample()</a>, <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>, <a class="el" href="xi3c__polled__example_8c.html#a6d80b58793a1c3b19f6b5afb9da35009">I3cMasterPolledExample()</a>, <a class="el" href="group___overview.html#gaa01a28908016aac835dd4493a0c6413e">XI3C_BusInit()</a>, and <a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8bdcc22a96e0b2be5e806b29761cc83a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SetSClk </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>SclkHz</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Mode</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sets I3C Scl clock frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">SclkHz</td><td>is Scl clock to be configured in Hz. </td></tr>
    <tr><td class="paramname">Mode</td><td>is the mode of operation I2C/I3C.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The return value is XST_SUCCESS if successful.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c___config.html#afcc9598c42b89940e46ed396994f62cb">XI3c_Config::InputClockHz</a>, <a class="el" href="group___overview.html#ga34208c49e1fb181e5d75006a27cee535">XI3c_GetRevisionNumber</a>, <a class="el" href="group___overview.html#ga71c271412e577611810fe80fe0f51703">XI3C_OD_SCL_HIGH_TIME_OFFSET</a>, <a class="el" href="group___overview.html#ga5455e0616c1f4d0728b493ea0fb92b6f">XI3C_OD_SCL_LOW_TIME_OFFSET</a>, <a class="el" href="group___overview.html#ga19907a1f8fccab4045cec4f33a0a019b">XI3C_SCL_HIGH_TIME_OFFSET</a>, <a class="el" href="group___overview.html#gacac5bc3663c87ed53678bbb88c58a737">XI3C_SCL_LOW_TIME_OFFSET</a>, <a class="el" href="group___overview.html#gac98f0b52e9c9c40ccf5b41cd8fce94d6">XI3C_SDA_HOLD_TIME_OFFSET</a>, <a class="el" href="group___overview.html#ga7b6019d7d90a6ffe16d5031c677da546">XI3C_THD_START_OFFSET</a>, <a class="el" href="group___overview.html#gaad8bc7285bee2d4b07caf0be75751909">XI3C_TSU_START_OFFSET</a>, <a class="el" href="group___overview.html#gaf9c766c72c30099de526c5d78a99ba5c">XI3C_TSU_STOP_OFFSET</a>, and <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>.</p>

</div>
</div>
<a class="anchor" id="gaa8b632c4926c7125ffe178ec72a167db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_SetStatusHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group___overview.html#ga7a0b155b789c03dd574c94bbf0d195db">XI3c_IntrHandler</a>&#160;</td>
          <td class="paramname"><em>FunctionPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function sets the status handler, which the driver calls when it encounters conditions that should be reported to the higher layer software. </p>
<p>The handler executes in an interrupt context, so the amount of processing should be minimized</p>
<p>Refer to the xi3c.h file for a list of events. The events are defined to start with XI3C_EVENT_*.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">FunctionPtr</td><td>is the pointer to the callback function.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>The handler is called within interrupt context, so it should finish its work quickly. </p>

<p>References <a class="el" href="struct_x_i3c.html#a50fcb290a96dc55a925ae6609ac639f5">XI3c::IsReady</a>, and <a class="el" href="struct_x_i3c.html#a42264face85bd7505cf2eef5b1d173c8">XI3c::StatusHandler</a>.</p>

<p>Referenced by <a class="el" href="xi3c__intr__example_8c.html#a78f3810e0c23ac76fc4ab526a5e5ebb9">I3cMasterIntrExample()</a>, and <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga64fba1f66dc69a20b21f414cccb90752"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_SlaveInterruptHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The interrupt handler for the slave mode. </p>
<p>It does the slave side protocol handling for the interrupt-driven transfers.</p>
<p>If the slave is receiving data then the data is read from the FIFO and the slave has to send data on master request data need to write to FIFO. If all the data has been transferred then a completion event is signalled to the upper layer by calling the callback handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#a93ed676334e0e5f04dda3550f6579922">XI3c::DirectCCC</a>, <a class="el" href="struct_x_i3c.html#a0c086a67f034487baa4ea845f7a35a13">XI3c::Error</a>, <a class="el" href="struct_x_i3c.html#a42264face85bd7505cf2eef5b1d173c8">XI3c::StatusHandler</a>, <a class="el" href="group___overview.html#gabdb31954696a689f6a99d67ec180e6e7">XI3C_INTR_RESP_NOT_EMPTY_MASK</a>, <a class="el" href="group___overview.html#ga8db15484dd9ba5bbfcd041249b63ef4c">XI3C_INTR_STATUS_OFFSET</a>, <a class="el" href="group___overview.html#gab12a89030f0016bebe64fac8878cc57f">XI3c_ReadReg</a>, and <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga9808772192d0f16adaf33e61b784e3a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SlaveRecv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a interrupt mode receive in slave mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the recv buffer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_NO_DATA if MsgPtr is NULL.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>.</p>

<p>Referenced by <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="gac5999cb023a2ac9ca5dea7a9ed3edda5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SlaveRecvPolled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a polled mode receive in slave mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_RECV_ERROR if any error.</li>
<li>XST_NO_DATA if MsgPtr is NULL.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c.html#a3f6c4ec1591de0e048f2888c7762536c">XI3c::RecvBufferPtr</a>.</p>

<p>Referenced by <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga28021172cfe5d1d3dfb20e8f3f58c94f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SlaveSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a interrupt mode send in slave mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>- XST_SUCCESS if everything went well.<ul>
<li>XST_NO_DATA if MsgPtr is NULL.<ul>
<li>Error code if any error.</li>
</ul>
</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c___config.html#a1ccd35fbd357de82147eed63989ede57">XI3c_Config::RwFifoDepth</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd">XI3c_FillSlaveSendCount</a>, <a class="el" href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25">XI3c_GetMRL</a>, <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__slave__intr__example_8c.html#aabd9a17bad898a69a8cf81b2d25a3933">I3cSlaveIntrExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">s32 XI3c_SlaveSendPolled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>MsgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>ByteCount</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function initiates a polled mode send in slave mode. </p>
<p>It sends data to the FIFO and the master to pick them up.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_i3c.html" title="The XI3c driver instance data. ">XI3c</a> instance. </td></tr>
    <tr><td class="paramname">MsgPtr</td><td>is the pointer to the send buffer. </td></tr>
    <tr><td class="paramname">ByteCount</td><td>is the number of bytes to be sent.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if everything went well.</li>
<li>XST_SEND_ERROR if any error.</li>
<li>XST_NO_DATA if MsgPtr is NULL.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Caller need to wait for response after calling this function. </dd></dl>

<p>References <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c___config.html#a1ccd35fbd357de82147eed63989ede57">XI3c_Config::RwFifoDepth</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#ga2577bc2333d12a6bd75e2a79442f90bd">XI3c_FillSlaveSendCount</a>, <a class="el" href="group___overview.html#gab50db6a1880449022a970ccb4d8a6d25">XI3c_GetMRL</a>, <a class="el" href="group___overview.html#ga0a979344e276171bf0bf87eb27c7ffd7">XI3c_WrFifoLevel</a>, and <a class="el" href="group___overview.html#ga58e612565bbd976e98eac6753ad1ed9f">XI3c_WriteTxFifo()</a>.</p>

<p>Referenced by <a class="el" href="xi3c__slave__polled__example_8c.html#a70498edac38d02a068cbe0f105d5ac45">I3cSlavePolledExample()</a>.</p>

</div>
</div>
<a class="anchor" id="ga58e612565bbd976e98eac6753ad1ed9f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XI3c_WriteTxFifo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_i3c.html">XI3c</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fill I3C Write Tx FIFO. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>contains the base address of the device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_i3c___config.html#a5022354efb94520441dca651cb9643bc">XI3c_Config::BaseAddress</a>, <a class="el" href="struct_x_i3c.html#a8a4d3a8c73221b302c6eedbdb4496b71">XI3c::Config</a>, <a class="el" href="struct_x_i3c.html#aacf49fb0c5aefd9418f78549e9393a8d">XI3c::SendBufferPtr</a>, <a class="el" href="struct_x_i3c.html#a7a73acb245300e5187a609fffae9358b">XI3c::SendByteCount</a>, <a class="el" href="group___overview.html#ga38756ab021295465c1b621deb8d80ec2">XI3C_WR_FIFO_OFFSET</a>, and <a class="el" href="group___overview.html#ga6d1adc84977bc35bde5d82bb4a874d6b">XI3c_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="group___overview.html#ga87d285dd413cf579d43a6eda306619ce">XI3c_DynaAddrAssign()</a>, <a class="el" href="group___overview.html#ga8c4e3e321553508d75097bebe04d0cf5">XI3c_MasterInterruptHandler()</a>, <a class="el" href="group___overview.html#gab0d816198d0abc6dabb332390fbe5c79">XI3c_MasterSend()</a>, <a class="el" href="group___overview.html#ga268011500642adc668ce75abbe555a6a">XI3c_MasterSendPolled()</a>, <a class="el" href="group___overview.html#ga822775f0526bd47739bdf842954d874f">XI3c_SendTransferCmd()</a>, <a class="el" href="group___overview.html#ga28021172cfe5d1d3dfb20e8f3f58c94f">XI3c_SlaveSend()</a>, and <a class="el" href="group___overview.html#ga7aafe3b5f4c0b20e5f6d8b7364c9ea4a">XI3c_SlaveSendPolled()</a>.</p>

</div>
</div>
<h2 class="groupheader">Variable Documentation</h2>
<a class="anchor" id="ga5f1a8c5c110ac26b11c3c77fa1f39f57"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a> XI3c_ConfigTable[XPAR_XI3C_NUM_INSTANCES]</td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Initial value:</b><div class="fragment"><div class="line">= {</div>
<div class="line">        {</div>
<div class="line">                (u16)XPAR_XI3C_0_DEVICE_ID, </div>
<div class="line">                (u32)XPAR_XI3C_0_BASEADDR,  </div>
<div class="line">                (u32)XPAR_XI3C_0_I3C_CLK_FREQ_HZ, </div>
<div class="line">                (u32)XPAR_XI3C_0_RW_FIFO_DEPTH, </div>
<div class="line">                (u32)XPAR_XI3C_0_WRITE_FIFO_THRESHOLD, </div>
<div class="line">                (u32)XPAR_XI3C_0_DEVICE_COUNT, </div>
<div class="line">                (u32)XPAR_XI3C_0_IBI_CAPABLE, </div>
<div class="line">                (u32)XPAR_XI3C_0_HJ_CAPABLE </div>
<div class="line">                (u32)XPAR_XI3C_0_DEVICE_ROLE </div>
<div class="line">        },</div>
<div class="line">        {</div>
<div class="line">                (u16)XPAR_XI3C_1_DEVICE_ID, </div>
<div class="line">                (u32)XPAR_XI3C_1_BASEADDR,  </div>
<div class="line">                (u32)XPAR_XI3C_1_I3C_CLK_FREQ_HZ, </div>
<div class="line">                (u32)XPAR_XI3C_1_RW_FIFO_DEPTH, </div>
<div class="line">                (u32)XPAR_XI3C_1_WRITE_FIFO_THRESHOLD, </div>
<div class="line">                (u32)XPAR_XI3C_1_DEVICE_COUNT, </div>
<div class="line">                (u32)XPAR_XI3C_1_IBI_CAPABLE, </div>
<div class="line">                (u32)XPAR_XI3C_1_HJ_CAPABLE </div>
<div class="line">                (u32)XPAR_XI3C_1_DEVICE_ROLE </div>
<div class="line">        }</div>
<div class="line">}</div>
</div><!-- fragment -->
<p>This table contains configuration information for each I3C device in the system. </p>
<p>Configuration table. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8212bca3426c2ca6a284e5de2a5a9180">XI3c_LookupConfig()</a>.</p>

</div>
</div>
<a class="anchor" id="ga71e0cc721aa929d7f8e04206061d97c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname"><a class="el" href="struct_x_i3c___config.html">XI3c_Config</a> XI3c_ConfigTable[]</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configuration table. </p>
<p>Configuration table. </p>

<p>Referenced by <a class="el" href="group___overview.html#ga8212bca3426c2ca6a284e5de2a5a9180">XI3c_LookupConfig()</a>.</p>

</div>
</div>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
